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【正文】 附錄 A 科技文章摘譯 MICROPROCESSOR REPORT Atmel AVR Brings RISC to 8Bit World Better Performance Than Other 8Bit Chips With Same Low Cost By Jim Turley Proving the adage that all technologies eventually filter down into modity products, Atmel has brought RISC design philosophy to 8bit microcontrollers. Dubbed AVR, this new architecture provides all the usual benefits of RISC: faster clock rates, better performance, and more efficient piler optimization. Atmel also promises better code density and lower cost than parable 8bit microcontrollers. AVR petes with several wellestablished microcontroller dynasties such as the 6805, 68HC11, and also es from Microchip’s PIC family, a more modern design that’s expanded rapidly in the past few years. Atmel hopes AVR will appeal to embedded designers who are willing to tackle a new architecture to get more performance than the entrenched microcontroller families can provide. AVR is the first inhouse CPU design from Atmel, a billiondollar pany better known for its flash memory and E2PROM products. The pany also sells a dozen flashbased derivatives of the popular 8051family, which it produces under license from Intel. Design Melds RISC and Microcontroller Ideas The CPU resembles most RISC processors but has smaller registers. It was originally developed by a pair of researchers in Trondheim,Norway, before their consultancy was acquired by Atmel in 1995. Core CPU development still takes place in Norway, while memory and peripheral development is centered in Atmel’s San Jose (Calif.) facility. The core features 32 identical 8bit registers, as Figure 1 shows. Any register can hold addresses or data. Since 8bit address pointers are fairly worthless even in an 8bit device, the last six registers can be used in pairs, as address pointers. Dubbed X, Y, and Z, these three metaregisters can be used for any load or store operation. The pointers can be post incremented or predecremented at the programmer’s option. Finally, a 6bit displacement can be added to the contents of the pointer, a useful option for addressing array elements. This mode is not available for the X pointer。 that op code is reserved for the LDI (load immediate constant) instruction. Figure 1. Unlike other 8bit controllers, AVR has a set of 32 8bit registers. The last six registers can be paired to form three address pointers. As with many lowend microcontrollers, the register file is mapped into the address space, and vice versa. The first 32 bytes of memory, 0x00–0x1F, correspond to registers R0–R31. The chip’s status register—which contains the overflow, carry, sign, and other flags—as well as other ―internal‖ registers are also memory mapped. This allows any register to be manipulated using standard memory references instead of special controlregister instructions. For all intents and purposes, the CPU has no pipeline. It retrieves both source operands, executes the instruction, and stores the result in a single clock cycle. Branch latency is one clock for taken branches. All operations are registertoregister。 the chip follows a strict load/store model. The great majority of AVR instructions
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