半導(dǎo)體制造裝備概述(已改無(wú)錯(cuò)字)
2023-03-17 08:37:15 本頁(yè)面
【正文】 lure during pull test may occur at one of the five positions in the wirebond structure: A. Lift off first bond B. Wire break at transition first bond C. Wire break mid span D. Wire break at transition second bond E. Lift off second bond When properly pulled, the bond should fail at B or D. If failures occur at A, C, or E, then the bonding parameters, metallization, bonding machine, bonding tool, hook, has to be reviewed. 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 FlipChip Technology 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 Advantages: Smaller size: Smaller IC footprint (only about 5% of that of packaged IC . quad flat pack), reduced height and weight. Increased functionality: The use of flip chips allow an increase in the number of I/O. I/O is not limited to the perimeter of the chip as in wire bonding. An area array pad layout enables more signal, power and ground connections in less space. A flip chip can easily handle more than 400 pads. Improved performance: Short interconnect delivers low inductance, resistance and capacitance, small electrical delays, good high frequency characteristics, thermal path from the back side of the die. Improved reliability: Epoxy underfill in large chips ensures high reliability. Flipchips can reduce the number connections per pin from three to one. Improved thermal capabilities: Because flip chips are not encapsulated, the back side of the chip can be used for efficient cooling. Low cost: Batch bumping process, cost of bumping decreases, cost reductions in the underfillprocess 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 Disadvantages: Difficult testing of bare dies. Limited availability of bumped chips. Challenge for PCB technology as pitches bee very fine and bump counts are high. For inspection of hidden joints an Xray equipment is needed. Weak process patibility with SMT. Handling of bare chips is difficult. High assembly accuracy needed. With present day materials underfilling process with a considerable curing time is needed. Low reliability for some substrates. Repairing is difficult or impossible. 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 底部填充工藝 (Underfilling Process） 溫度膨脹系數(shù)小于 3 ppm/℃ 的硅器件直接同有機(jī)物印制線路板 (溫度膨脹系數(shù)在 1 8～ 50 ppm/℃ )壓接在一起 ,會(huì)產(chǎn)生嚴(yán)重的 熱機(jī)應(yīng)力和疲勞 ,俗稱(chēng)“熱機(jī)失配 底部填充料鎖住倒裝片和印制板示意圖 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 Flip chip joining using adhesives (isotropic, anisotropic, nonconductive) 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 Flip chip joining by thermopression. Flip chip thermosonic joining 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 Flip chip bonding using thermopression 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 Flip chip process by solder joining die preparing (testing, bumping, dicing) substrate preparing (flux application or solder paste printing) pick, alignment and place reflow soldering cleaning of flux residues (optional) underfill dispensing underfill curing. 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 華中科技大學(xué) 機(jī)械學(xué)院 機(jī)械電子信息工程系 Flip chip joining using adhesives 華中科技大學(xué) 機(jī)械學(xué)院
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