嵌入式系統(tǒng)應(yīng)用--adc--模擬電壓采集-肖迎春(已改無錯(cuò)字)
2023-06-24 07:26:34 本頁面
【正文】 lt Channel2 conversion result Channel3 conversion result Channel4 conversion result Channel5 conversion result Channel6 conversion result Channel7 conversion result Channel8 conversion result ADC1 DR register . . . DMA Request DMA Request DMA Request DMA Request DMA Request DMA Request DMA Request DMA Request ConvertedValue_Tab[9] Note: EOC flag cleared at end of regular channels conversion due to DMA access to ADC1 DR register 29 ADC dual modes (1/9) ? Available in devices with two ADCs: ADC1 master and ADC2 slave ? ADC1 and ADC2 triggers are synchronized internally for regular and injected channels conversion ? 8 ADC dual modes GPIO Ports Temp Sensor VREFINT Up to 4 injected channels Up to 16 regular channels ADC_IN0 ANALOG MUX … ADC_IN1 ADC_IN15 ADC1 Analog ADC2 Analog Digital Master Digital Slave External ev ent synchronization External ev ent (Regular group) External ev ent (Injected group) Data register EOC/JEOC … 30 ADC dual modes (2/9) Injected simultaneous mode CH0 CH1 CH2 CH3 CH15 CH13 CH1 CH2 ? Converts an injected channel group ? The external trigger source, which start the conversion, es from ADC1 (simultaneous trigger provided to ADC2) ? An end of injected conversion is generated at the end of all channels conversion ? Results stored on injected data registers of each ADC. Note: Do not convert the same channel on the two ADCs ADC2 ADC1 Injected simultaneous mode on 4 injected channels Sampling Conversion Trigger for injected channels End of Injected Conversion on ADC1 and ADC2 31 ADC dual modes (3/9) Regular simultaneous mode CH0 CH1 CH2 CH3 CH15 CH14 CH13 CH12 ? Converts a regular channel group ? The external trigger source, which start the conversion, es from ADC1 (simultaneous trigger provided to ADC2) ? An end of conversion is generated at the end of all channels conversion ? Results stored on ADC1 regular data register (32bits) Note: Do not convert the same channel on the two ADCs ADC2 ADC1 Regular simultaneous mode on 16 regular channels Sampling Conversion Trigger for regular channels End of Conversion on ADC1 and ADC2 … … CH15 CH0 32 ADC dual modes (4/9) Fast Interleaved mode CH0 CH0 ? Converts a regular channel group (usually one channel) ? The external trigger source, which start the conversion, es from ADC1: ? ADC2 starts immediately on ADC1 trigger ? ADC1 starts after a delay of 7 ADC clock cycles ? An end of conversion is generated at the end of all channels conversion ? Results stored on ADC1 regular data register (32bits) ADC2 ADC1 Fast Interleaved mode on 1 regular channel in continuous conversion mode Sampling Conversion Trigger for regular channels End of Conversion on ADC1 7 ADCCLK cycles … … CH0 CH0 CH0 CH0 End of Conversion on ADC2 Note: The maximum sampling time allowed is less than 7 ADC clock cycles 33 ADC dual modes (5/9) Slow Interleaved mode CH0 CH0 ? Converts a regular channel group (only one channel) ? The external trigger source, which start the conversion, es from ADC1: ? ADC2 starts immediately on ADC1 trigger ? ADC1 starts after a delay of 14 ADC clock cycles ? An end of conversion is generated at the end of all channels conversion ? Results stored on ADC1 regular data register (32bits) ? A new ADC2 start is automatically generated after 28 ADC clock cycles Note: The maximum sampling time allowed is less than 14 ADC clock cycles Continuous conversion mode is not supported ADC2 ADC1 Slow Interleaved mode on 1 regular channel Sampling Conversion Trigger for regular channel End of Conversion on ADC1 14 ADCCLK cycles CH0 CH0 28 ADCCLK cycles End of Conversion on ADC1 34 ADC dual modes (6/9) Alternate Trigger mode CH0 ? Converts an injected channel group ? The external trigger source, which start the conversion, es from ADC1 (in case of injected discontinuous mode enabled): ? On 1st trigg
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