嵌入式系統(tǒng)應(yīng)用--adc--模擬電壓采集-肖迎春-文庫(kù)吧在線文庫(kù)
【正文】 Div2, Div4, Div6 and Div8 PCLK2 cycles cycles cycles cycles cycles cycles cycles cycles Sample Time Selection SMPx[2:0] 24 ADC conversion modes ? Four conversion mode are available: CHx Start Stop CHx Start Stop . . . CHn CHx Start CHx Start . . . CHn Single channel single conversion mode Multichannels (Scan) single conversion mode Multichannels (Scan) continuous conversion mode Single channel continuous conversion mode 25 ADC discontinuous conversion mode ? Split channels conversion sequence into subsequences ? Available for both regular and injected groups: ? Up to 8 conversion for regular channel ? 1 conversion for injected channel Example: Conversion of channels: 0, 1, 2, 4, 5, 8, 9, 11, 12, 13, 14 and 15 Discontinuous mode Number of channel is 3 Channel0 Channel1 Channel2 Channel4 Channel5 Channel8 Channel9 Channel11 Channel12 Channel13 Channel14 Channel15 1st trigger 2nd trigger 3rd trigger 4th trigger End of Conversion Channel0 Channel1 Channel2 5th trigger … Note: Do not use discontinuous mode for both regular and injected together. It can be used only for one group channel 26 ADC Data alignment ? One bit data align selection: right or left ? For injected channel conversion negative value after subtraction of the offset the sign is extended in right alignment SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Right alignment 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SEXT 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Left alignment 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Regular group Injected group Regular group Injected group 27 ADC Analog Watchdogs ? 12bit programmable analog watchdog low and high thresholds ? Enabled on one, some or all converted channels: one regular or/and injected channel, all injected or/and regular channels. ? Interrupt generation on low or high thresholds detection Status Register Analog Watchdog Low Threshold Temp Sensor VREFINT ADC_IN0 ADC_IN1 ADC_IN15 . . . AWD High Threshold 28 DMA ? DMA available only on ADC1 ? DMA request generated on each ADC1 end of regular channel conversion (Not in injected channels) Example: Conversion of regular channels: 0, 1, 2, 3, 4, 5, 6, 7 and 8 Converted ata stored in ConvertedValue_Tab[9] DMA transfer enabled (destination address auto incremented) Channel0 Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7 Channel8 DMA Request Channel0 conversion result Channel1 conversion result Channel2 conversion result Channel3 conversion result Channel4 conversion result Channel5 conversion result Channel6 conversion result Channel7 conversion result Channel8 conversion result ADC1 DR register . . . DMA Request DMA Request DMA Request DMA Request DMA Request DMA Request DMA Request DMA Request ConvertedValue_Tab[9] Note: EOC flag cleared at end of regular channels conversion due to DMA access to ADC1 DR register 29 ADC dual modes (1/9) ? Available in devices with two ADCs: ADC1 master and ADC2 slave ? ADC1 and ADC2 triggers are synchronized internally for regular and injected channels conversion ? 8 ADC dual modes GPIO Ports Temp Sensor VREFINT Up to 4 injected channels Up to 16 regular channels ADC_IN0 ANALOG MUX … ADC_IN1 ADC_IN15 ADC1 Analog ADC2 Analog Digital Master Digital Slave External ev ent synchronization External ev ent (Regular group) External ev ent (Injected group) Data register EOC/JEOC … 30 ADC dual modes (2/9) Injected simultaneous mode CH0 CH1 CH2 CH3 CH15 CH13 CH1 CH2 ? Converts an injected channel group ? The external trigger source, which start the conversion, es from ADC1 (simultaneous trigger provided to ADC2) ? An end of injected conversion is generated at the end o
醫(yī)療健康相關(guān)推薦
鄂ICP備17016276號(hào)-1