【正文】 f all channels conversion ? Results stored on injected data registers of each ADC. Note: Do not convert the same channel on the two ADCs ADC2 ADC1 Injected simultaneous mode on 4 injected channels Sampling Conversion Trigger for injected channels End of Injected Conversion on ADC1 and ADC2 31 ADC dual modes (3/9) Regular simultaneous mode CH0 CH1 CH2 CH3 CH15 CH14 CH13 CH12 ? Converts a regular channel group ? The external trigger source, which start the conversion, es from ADC1 (simultaneous trigger provided to ADC2) ? An end of conversion is generated at the end of all channels conversion ? Results stored on ADC1 regular data register (32bits) Note: Do not convert the same channel on the two ADCs ADC2 ADC1 Regular simultaneous mode on 16 regular channels Sampling Conversion Trigger for regular channels End of Conversion on ADC1 and ADC2 … … CH15 CH0 32 ADC dual modes (4/9) Fast Interleaved mode CH0 CH0 ? Converts a regular channel group (usually one channel) ? The external trigger source, which start the conversion, es from ADC1: ? ADC2 starts immediately on ADC1 trigger ? ADC1 starts after a delay of 7 ADC clock cycles ? An end of conversion is generated at the end of all channels conversion ? Results stored on ADC1 regular data register (32bits) ADC2 ADC1 Fast Interleaved mode on 1 regular channel in continuous conversion mode Sampling Conversion Trigger for regular channels End of Conversion on ADC1 7 ADCCLK cycles … … CH0 CH0 CH0 CH0 End of Conversion on ADC2 Note: The maximum sampling time allowed is less than 7 ADC clock cycles 33 ADC dual modes (5/9) Slow Interleaved mode CH0 CH0 ? Converts a regular channel group (only one channel) ? The external trigger source, which start the conversion, es from ADC1: ? ADC2 starts immediately on ADC1 trigger ? ADC1 starts after a delay of 14 ADC clock cycles ? An end of conversion is generated at the end of all channels conversion ? Results stored on ADC1 regular data register (32bits) ? A new ADC2 start is automatically generated after 28 ADC clock cycles Note: The maximum sampling time allowed is less than 14 ADC clock cycles Continuous conversion mode is not supported ADC2 ADC1 Slow Interleaved mode on 1 regular channel Sampling Conversion Trigger for regular channel End of Conversion on ADC1 14 ADCCLK cycles CH0 CH0 28 ADCCLK cycles End of Conversion on ADC1 34 ADC dual modes (6/9) Alternate Trigger mode CH0 ? Converts an injected channel group ? The external trigger source, which start the conversion, es from ADC1 (in case of injected discontinuous mode enabled): ? On 1st trigger, the first injected group channel in ADC1 is converted ? On 2nd trigger, the first injected group channel in ADC2 is converted ? On 3rd trigger, the second injected group channel in ADC1 is converted ? … ? An end of injected conversion is generated at the end of all channels conversion ? Results stored on injected data registers of each ADC. ADC1 ADC2 Alternate Trigger mode on 4 injected channels (injected discontinuous mode enabled) Sampling Conversion 2nd Trigger JEOC on ADC2 CH11 CH1 CH12 CH13 CH2 CH3 1st Trigger 4th Trigger 6th Trigger 8th Trigger 3rd Trigger 5th Trigger 7th Trigger CH10 JEOC on ADC1 35 ADC dual modes (7/9) Combined Regular/Injected simultaneous mode CH0 CH1 CH1 CH2 CH3 CH2 CH2 CH1 ? Converts an injected and a regular channels groups ? The external triggers sources, which start the conversions, es from ADC1 (simultaneous trigger provided to ADC2): injected simultaneous mode can interrupt the other one ? An end of injected conversion is generated at the end of all injected channels conversion and an end of conversion is generated at the end of all regular channels ? Results of injected channels stored on injected data registers of each ADC, and regular channels on ADC1 data register (32bits) Note: Do not convert the same channel on the two ADCs ADC2 ADC1 Combined