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1111111122222222222222222223333333333333333333333555555555554444444444444444888888888881234585447998884512345854479988845123458533333N(模數(shù))35566224568997441254231556874912554549125545231556874912554523155687315568745525771123155687491255454912554523155687491255452315568731556874552577115568745525771112554549125545231556812554549125545231556812554549125545231556812554549125545231556845525771155687455257711125545491255452315568125545491255452315568125545491255452345525771155687455257711125545491255452315568125545491255452315568125545491255452345525771155687455257711125545491255452315568125545491255452315568125545491255452345525771155687455257713R134DF2AF20EA713703B16B01BCDFD8EB803A9040923E427FC358AC9D69623D7D8C032E6E95887ED5622C8E69660C0FCC2646E8CE0637DB0D6F5FA07C7A91B939CC83EDDF00D4A336D4B8F224E749EDD05B569B6CD46F27DC75D61C79802EFF0C6F93FA424CFEB9BC9009AA6C14B14E1A2600822530CB84178EF81282570E446302E5DA22952345D2B253A3DE8601B1A230179141D54B324FD9E5D37624A403DAAAFDF93673C4D129C8B3E465BD2361BA0948505956F477CC7D47FB1A621CDC05A85551ECF23CFBE454708DC8212B6FC639CED14202D51C2FEA41799139FECA831E24313809BEF4FEDC7D4AC1C034E26B05EFE9A76D866AF8AA3A4F3AE2E5D4792預(yù)期結(jié)果072281D35CA3EF82583578712CC5FFDFDC73BDD0B39211CDAA866E0DCC8A40724626FA81CE9A7F86391CA0140C12AA150B2CEFC7E9C568473E1AFEAA1223F93F1E0B465BAB7DB0CDCE077913DA914204026741FC6B2163EF389BC274A463F496B843D64E1375C6CEAE8BDC29AFA093340B8B082FCD83E07C6352744459454F95BDE645B57C1D084A872A984602D4E781BC89C98EE403B1CA008F44875CF9FAD4AFE7EB71E568BFD0240FE5FCA94C733A9E37E3B52F07CB9901AB986B6C13C10A71541105EB599C2CDD1A6CFAB9FD6BA60778A6EF5FC1E31DD3C9E8D1DD771692C6B423D8E81EB20258DEF12BEB99FDC5B1A3769530E576A19EDD6A14CC1E99A9實(shí)際結(jié)果072281D35CA3EF82583578712CC5FFDFDC73BDD0B39211CDAA866E0DCC8A40724626FA81CE9A7F86391CA0140C12AA150B2CEFC7E9C568473E1AFEAA1223F93F1E0B465BAB7DB0CDCE077913DA914204026741FC6B2163EF389BC274A463F496B843D64E1375C6CEAE8BDC29AFA093340B8B082FCD83E07C6352744459454F95BDE645B57C1D084A872A984602D4E781BC89C98EE403B1CA008F44875CF9FAD4AFE7EB71E568BFD0240FE5FCA94C733A9E37E3B52F07CB9901AB986B6C13C10A71541105EB599C2CDD1A6CFAB9FD6BA60778A6EF5FC1E31DD3C9E8D1DD771692C6B423D8E81EB20258DEF12BEB99FDC5B1A3769530E576A19EDD6A14CC1E99A92048規(guī)格前仿真波形圖如下: 2048規(guī)格模冪乘前仿真波形圖 小結(jié)1) 運(yùn)用Montgomery算法,在每次循環(huán)結(jié)束后得到的結(jié)果Zi+1必需和N進(jìn)行比較,比N大的話,還要進(jìn)行Zi+1=Zi+1 – 1的運(yùn)算,否則不一定能得到正確結(jié)果,這是Montgomery算法的一局限性。2) 無(wú)淪是用離散邏輯、可編程邏輯,還是用全定制硅器件實(shí)現(xiàn)的任何數(shù)字設(shè)計(jì),為了成功地操作,可靠的時(shí)鐘是非常關(guān)鍵的。時(shí)鐘可分為如下四種類型:全局時(shí)鐘、門控時(shí)鐘、多級(jí)邏輯時(shí)鐘和波動(dòng)式時(shí)鐘。在我設(shè)計(jì)的模冪乘電路中,有很多觸發(fā)器的CLK時(shí)鐘不統(tǒng)一(時(shí)鐘正負(fù)沿沒(méi)有統(tǒng)一的設(shè)計(jì)),這樣設(shè)計(jì)出來(lái)的電路穩(wěn)定性差。 FPGA測(cè)試 FPGA測(cè)試環(huán)境簡(jiǎn)介運(yùn)用Quartus II進(jìn)行模冪乘IP的FPGA測(cè)試,如下圖所示, FPGA測(cè)試環(huán)境 FPGA環(huán)境搭建過(guò)程1)新建工程,設(shè)置完成工程名,芯片類型,仿真環(huán)境等,如下圖, 新建FPGA測(cè)試工程圖2)加載完成模冪乘電路編碼,并進(jìn)行語(yǔ)法編譯。在系統(tǒng)內(nèi)部取反便能得到相對(duì)于輸入時(shí)鐘的負(fù)沿時(shí)鐘。3) RS232接口輸出記錄設(shè)計(jì)一個(gè)RS232接口,把模冪乘結(jié)果從RS232接口輸出到PC機(jī)上,方便觀察記錄。 RS232接口外特性描述 FPGA下載界面2048位規(guī)格模乘結(jié)果:預(yù)期結(jié)果072281D35CA3EF82583578712CC5FFDFDC73BDD0B39211CDAA866E0DCC8A40724626FA81CE9A7F86391CA0140C12AA150B2CEFC7E9C568473E1AFEAA1223F93F1E0B465BAB7DB0CDCE077913DA914204026741FC6B2163EF389BC274A463F496B843D64E1375C6CEAE8BDC29AFA093340B8B082FCD83E07C6352744459454F95BDE645B57C1D084A872A984602D4E781BC89C98EE403B1CA008F44875CF9FAD4AFE7EB71E568BFD0240FE5FCA94C733A9E37E3B52F07CB9901AB986B6C13C10A71541105EB599C2CDD1A6CFAB9FD6BA60778A6EF5FC1E31DD3C9E8D1DD771692C6B423D8E81EB20258DEF12BEB99FDC5B1A3769530E576A19EDD6A14CC1E99A9實(shí)際結(jié)果072281D35CA3EF82583578712CC5FFDFDC73BDD0B39211CDAA866E0DCC8A40724626FA81CE9A7F86391CA0140C12AA150B2CEFC7E9C568473E1AFEAA1223F93F1E0B465BAB7DB0CDCE077913DA914204026741FC6B2163EF389BC274A463F496B843D64E1375C6CEAE8BDC29AFA093340B8B082FCD83E07C6352744459454F95BDE645B57C1D084A872A984602D4E781BC89C98EE403B1CA008F44875CF9FAD4AFE7EB71E568BFD0240FE5FCA94C733A9E37E3B52F07CB9901AB986B6C13C10A71541105EB599C2CDD1A6CFAB9FD6BA60778A6EF5FC1E31DD3C9E8D1DD771692C6B423D8E81EB20258DEF12BEB99FDC5B1A3769530E576A19EDD6A14CC1E99A9 小結(jié) 在用FPGA測(cè)試過(guò)程中,出現(xiàn)有很多奇怪問(wèn)題,例如在Modlesim前仿真沒(méi)有出現(xiàn)任何問(wèn)題,然而同樣的電路下載到FPGA后,測(cè)出來(lái)結(jié)果就不一樣。后來(lái)用邏輯分析儀測(cè)信號(hào),才發(fā)現(xiàn)是由于FPGA芯片上的外圍電路的一個(gè)緩沖器的出了問(wèn)題,標(biāo)準(zhǔn)的說(shuō)是沒(méi)有把緩沖器的外特性弄清楚,導(dǎo)致數(shù)據(jù)從芯片輸出到PC接口上。參 考 文 獻(xiàn)[1] 夏宇聞. Verilog數(shù)字系統(tǒng)設(shè)計(jì)教程. 北京:航天航空大學(xué)出版社,2005.[2] :郵電大學(xué)出版社,2005.[3] 劉大力 ,MISC體系結(jié)構(gòu)計(jì)算機(jī)的理論與方法,The 9th International Conference on Advanced Science and Technology, , P16P26 .[4] 戴大為,吳逵,張煥國(guó),有限自動(dòng)機(jī)公開(kāi)鑰密碼體制的密碼分析,中國(guó)科學(xué)(A輯),,1995,P1226P1232.[5] 李鍵寶,(第二界中國(guó)密碼學(xué)學(xué)術(shù)會(huì)議論文集).北京:科學(xué)出版社,1992.[6] :清華大學(xué)出版社,1998.[7] 楊之廉,:清華大學(xué)出版社, 2002.[8] Rivest R. Shamir A. Adleman L, A Method for Obtaining Digital Signatures and Publickey Cryptosystem., Communications of the ACM,, ,pp120~126.[9] and , New directions in cryptography. IEEE Trasactions on information theory, ,pp644~654.[10] 楊義先,陳明奇,毛瓊,“信息安全新秀——量子密碼學(xué)”,中國(guó)計(jì)算機(jī)報(bào),.[11] 胡勁松,陳國(guó)良,郭光燦,“在量子計(jì)算機(jī)上求解0/1背包問(wèn)題”, 計(jì)算機(jī)學(xué)報(bào), ,,pp1314~1316.[12] , and , A new publicKey cipher system base upon the Diophantine equations,IEEE, trasactions on puter, ,, pp13~19.[13] , Cryptanalysis of a Diophantine equation oriented public key cryptosystem, IEEE, trasactions on puter, ,,pp511~512.[14] ,and , A ment on ‘A new publicKey cipher system base upon the Diophantine equations’, IEEE, trasactions on puter, ,pp512.[15] , A public key cryptosystem and a signature scheme base on discrete logarithms, IEEE trasactions on information theory, ,,July 1985,pp469~472.[16] Bruce Schneier 著,吳世忠,祝世雄,張文政 等譯, “應(yīng)用密碼學(xué)——協(xié)議、算法與C源程序”,機(jī)械工業(yè)出版社,2000.[17] Colin . Montgomery exponentiation needs no final subtractions. Electronics Letters, ,1999, pp1831~1832.[18] Gael Hachez, JeanJacques Quisquter. Montgomery Exponentiation with no Final Subtractions: Improved results. .[19] , Modular multiplication without trial division, Mathematics of putation, , ,APRIL 1985,pp519~521.附錄 高速模冪乘實(shí)現(xiàn)編碼VHD描述library IEEE。use 。centity MMC is port ( CLK : in STD_LOGIC。 E : in STD_LOGIC_VECTOR(1 downto 0 )。 MMUL_OV : in STD_LOGIC。 RAM9_ADDR : OUT STD_LOGIC_VECTOR(4 downto 0 )。 RAM3_ADDR : OUT STD_LOGIC_VECTOR(4 downto 0 )。 RAM9_WE : OUT STD_LOGIC。 S3_E : out STD_LOGIC