【正文】 票資料打印 、ＩＣ卡付費(fèi)、語音報(bào)話、和電腦串行通信等功能 。 華東交通大學(xué)畢設(shè)計(jì) 25 結(jié)束語 本次設(shè)計(jì)中我做了以下工作 ,收集資料， 方案論證到方案確定 并按確定方案進(jìn)行概要設(shè)計(jì) 。 在設(shè) 計(jì)過程中遇到了很多問題 如 ： 沒計(jì)編寫程序流程圖， 也 沒有按照先整體后部分的原則 結(jié)果出現(xiàn)思路非常不 清晰 。 仔細(xì)分析所編模塊的原理就開始編程，導(dǎo)致后來無法完成程序編寫。 ，顯得 雜亂無章 等等一系列問題 。 6.本設(shè)計(jì) 采用的是 LED 顯示，也存在很大的不足， 靈活性比較差，不便于升級。 ，其實(shí)可以在譯碼輸出部分中多設(shè)置一個(gè)輸出控制模塊，用來進(jìn)行輸出內(nèi)容的選擇控制，例如可以設(shè)置一個(gè)兩位 二進(jìn)制數(shù) choose 信號(hào) “ 00” ， 當(dāng)它為 00 時(shí)選擇輸出計(jì)時(shí)的時(shí)間，當(dāng)為“ 01” 選擇輸出費(fèi)用。這樣設(shè)計(jì)可以節(jié)省四個(gè)數(shù)碼管。 但 我也充分認(rèn)識(shí)到自身的許多 不足：基礎(chǔ)知識(shí)學(xué)得不夠扎實(shí)，缺乏綜合運(yùn)用及理論聯(lián)系實(shí)際的能力等 。 感謝你 在畢業(yè)設(shè)計(jì) 期間給與我的悉心指導(dǎo)和關(guān)懷！ 你 求學(xué)的嚴(yán)謹(jǐn)態(tài)度、孜孜不倦的探索精神 ， 令我受益終 生 。 CLA is the frequency divider circuit, the duty cycle through datal (x) adjust Frequency Divider and with initiated / Reset terminal (serial Reset). Simulation waveform is shown in figure 2. As can be seen from the map, switch to set up 10 models, when the arrival of 57 pulses, The module oclk from high to low end, a low level output signal. Vehicle modules (hereinafter referred FP) Packaging Figure 4. Module log Log module is a scale of 10, in addition to one step counter. The module can be prefabricated parameters, it is larger than the actual precast numerical terms, courtesy of a pulse every 500 meters. Decoding dynamic scan numerical terms will be sent to the display module. Prefabricated nonpressed decimal parameters. Therefore, the design must be counter binary state jumped from 1,010 to 1,111 over the past six. In the process of VHDL, and IF sentence is to be achieved. If km (3 downto 0) = 1001 then km:=km+ 0111 : Else km:=kin+1。 Log module carries the start / Reset terminal. With Select use the same parameters of prefabricated language. Milestone start and switches relationship, as shown in table 2. Log Module (hereinafter referred Mile) Packaging Figure 4. Table 2 Starting mileage (km) DIP switches (three) 000 001 010 011 100 101 110 111 Billing Module Billing module is a scale of 10, the addition of variable step counter. The module switch 基于 FPGA 的出租車計(jì)費(fèi)系統(tǒng)設(shè)計(jì) 30 prefabricated step, when certain parameters change prefabricated step. Billing module will also reduce the use of nonBCD, but not for one step. Thus, in nonpressed BCD adder to be adjusted Otherwise, it could result in over or exceed preset parameters higher than the wrong way. Computer used to imitate the AF signs here and in the establishment of a semi carry their signs, When cumulative and carry more than 9 or semi signs of 1, and the cumulative adjustment. If datal (3 downto 0), nine or datal (4) = 39。 then Datal (3 downto 0): =datal (3 downto 0) + 0110。 Of these, data (4) advanced to the semiplace mark. Start value and super price increases set up parameters as shown in Table 3 and Table 4. Billing Module (hereinafter referred MONEY) Packaging Figure4. Table 3 installed starting price Starting price (s) DIP switches (three) 001 010 011 100 101 110 111 Table 4 super price plus set up fees Super price increases (yuan) DIP switches (2) 00 01 10 11 Module By paragraph 107 of the LED digital display module and dynamic management decoding scan showed two ponents. paragraph 107 LED decoding digital control This design is used in paragraph 107 of a total digital cathode tube, in accordance with paragraph 107, 16 and 229 the number of code table shows the correlation between When_Else With_Select or VHDL language can be used to facilitate the achievement of their decoding. Figure 2 dynamic scanning display Dynamic scanning using the human visual staying principle,if not less than 24Hz frequency scanning. Eye on the scintillating display scanning pulse of the system by providing the corresponding external scanning signal circuit design, the key lies with the EC shows that he gathers data in the timing. Therefore circuit must provide synchronous pulse signal. Eight 229 counters are used here to provide synchronization pulse,VHDL procedures as follows: CIkl_label:PROCESS (scp) BEGIN IF scp 39。 one 39。 Sound IF。 left PROCESS Data revealed by the choice of control counter, VHDL procedures as follows : Temp=counterl when count= 000 else. . . Counter4 when count= 1011 else 華東交通大學(xué)畢設(shè)計(jì) 31 Milel when count= 100 else. . . Mile4 when count= 111。one39。039。 Display Module (hereinafter referred SHOW) Packaging Figure 4. This module is used by the two processes, and procedures in order to implement the process, a process which triggered a second resolution process. Integrated 3 Module FBI Functional module design has been pleted, Segments II use of the graphic editor (Graphic Editor) to the functional module (. sym) link. Because there Mile module Burr, it is not directly linked to and after class. portal of the output pulse signal delay circuit, with the original signal phase and the method can remove burrs. System toplevel schematic diagram shown in Figure 4. Chip definition can be directly edited. Editor in FloorPlan pin documents or under. Pins plete definition chosen device (EPM7128SIC8415), the translation after generation. Sof that. Pofreports and documents. . Access device pins report documents the use of available resources and the use of the device. Replacement of the device make it appropriate to achieve optimal allocation of resources. The general principle is to choose the device system resources used by the devices should not exceed 80% of its resources, in excess of 90%. Power system will increase instability. From the design of this device : the importation of some note in the report, only 16 output pins with the chip resource utilization was only 51%. have greater room for expansion. Figure 4 hardware design shows The design of the CP TaxiMeter counting pulses from the wheel speed sensor (dry spring).Pulse shaping evacuation counter on the device。 rectifier system, filtering, Supp