基于fpga的任意信號(hào)發(fā)生器設(shè)計(jì)外文翻譯-其他專業(yè)-閱讀頁(yè)
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【正文】 的值為 50 歐姆， R2 為 100 歐姆， C =1000pF。該參考電壓幾乎是一個(gè)沒有太多指數(shù)功能的三角波。 ADC 的輸入是四個(gè)不同寬度和峰值振幅的脈沖序列 。采樣率大約是每秒采樣 兆， （雖然前端和后斜采樣點(diǎn)的采樣 間隔是不一樣的）。 TDC 的原始數(shù)據(jù)都顯示在圖 5（ a）中。 圖 5 （ a） TDC 的原始數(shù)據(jù) (b)數(shù)字化波形 應(yīng)當(dāng)指出， TDC 的值不僅僅代表著采樣點(diǎn)的電壓水平，而且還代表著采樣時(shí)間。 B、指數(shù)參考電壓 RC 網(wǎng)絡(luò)的放電性能指數(shù)，可用于提高 ADC 的動(dòng)態(tài)范圍。參考電壓如圖 6 所示，它有一個(gè)很短的時(shí)間常數(shù)。（請(qǐng)注意，圖 6 和圖 7（ a）的示波器時(shí)間尺度不同，但它們的電壓表是相同的。該測(cè)試展示了一個(gè)以 兆 每秒的采樣速率的 6 位的測(cè)量范圍，而樣本的尾部坡道動(dòng)態(tài)范圍大約是 8 位。被動(dòng)的 RC網(wǎng)絡(luò)的斜坡電壓在本質(zhì) 上是非線性，這在有時(shí)被認(rèn)為是一種缺陷。在我們的例子中，指數(shù)電壓斜坡可進(jìn)一步用于增加測(cè)量的動(dòng)態(tài)范圍，這已經(jīng)成為一種優(yōu)勢(shì)。 4 總結(jié) 研究了基于 TDC的多采樣， 實(shí)施了低成本 FPGA和測(cè)試臺(tái)的 三個(gè)應(yīng)用：僅 TDC下的多通道的 FPGA， 僅在 ADC 下的 FPGA 和一個(gè)解串器“數(shù)字相位跟隨器”的討論。 FPGA 與連續(xù)變量（抵達(dá)時(shí)間和輸入電壓）直接相接，可以消除外部設(shè)備，并簡(jiǎn)化系統(tǒng)設(shè)計(jì)。 The Design of Digital Signal Generator Based on FPGA Signal sources with high accuracy and operational frequency are used in the field of research and application of modern electronic measuring technology. Digital signal represent the development with it being one of the most widely measuring technology in the field. With the development of FPGA in a large scale and the maturing of SOPC, design technology have provided theoretical basis and technology support for the design and realization of such signal generators. This design of digital signal generator for FPGA as the core, with the FPGA as to achieve the frequency, phase, preset and step, and plete the signal frequency and phase display. As used in the design of direct digital synthesis(DDS). Technology and effectively extends the use of FPGA output waveform of the frequency range to achieve the output of twoway highprecision phase of the sinusoidal signal, so that the system is stable and reliable. With EDA software for the system, using VHDL language, to meet the CNC system for machining higher demands. Experimental results show that the original part of the CNC system pared to the control circuit design using EDA technology makes the NC signal generator system with higher reliable, realtime, high operation speed and high integration. At the same time as EDA technology with insystem programmable FPGA chip feature, so the shift key signal generator is designed to change the same as the software, which brings the system to facilitate maintenance. Combined with FPGA to extend effectively the frequency range of theoutput waveform to achieve the output of twoway highprecision phase of the sinusoidal signal, so that the system is stable and reliable. Keywords: signal generator。 System On a Programmable Chip。 D. Holberg, CMOS Analog Circuit Design, Second Edition, New York, New York: Oxford University Press, 2021. [2] B. G. Tomov amp。 R. Sumner, ―A new concept for a multirange low cost calorimeter ADC,‖ in Nuclear Science Symposium and Medical Imaging Conference, 1994 IEEE Conference Record, 30 5 Nov. 1994 Page(s):999 1001 . [5] Jinyuan Wu, Zonghan Shi amp。 J. J. Williams, ―Highprecision TDC in an FPGA using a 192 MHz quadrature clock,‖ in Nuclear Science Symposium Conference Record, 2021 IEEE, 1016 Nov. 2021 Page(s):580 – 584 vol. 1. [8] Altera Corp., ―Cyclone FPGA Family Data Sheet‖, (2021) available via: { [9] Altera Corporation, ―Cyclone II Device Handbook‖, (2021) available via: { [10] Jinyuan Wu, ―Digital Phase Follower Deserializer in LowCost FPGA‖, BTeV Document 3295v1, Fermi National Accelerator Laboratory, (2021), available online: { public/DocDB/ShowDocument?docid=3295} [11] Nick Sawyer, ―Data Recovery‖, Xilinx Application Note 224, (2021), available via: { [12] Jinyuan Wu, ―How to Design Compact FPGA Functions—Resource Awareness Design Practices‖, (2021) available via: { W/Projects/ckm/adc/ }
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