【正文】 //asyn write ptralways(posedge wclk or negedge wrst_n)begin if(!wrst_n) {w2_rptr,w1_rptr} = 239。 else {w2_rptr,w1_rptr} = {w1_rptr,rptr}。b00。end//assign waddr = wbin[(DEPTH1):0]。assign wgnext = (wbnext 1) ^ wbnext。always(posedge wclk or negedge wrst_n)begin if(!wrst_n) full_r = 139。 else full_r = full_val。b00。end/////generate rbin and rptralways(posedge rclk or negedge rrst_n)begin if(!rrst_n) {rbin,rptr} = 239。 else {rbin,rptr} = {rbnext_r,rgnext_r}。assign rbnext = !empty ? (rbin + !rinc) :rbin。assign empty_val = (rgnext_r == r2_wptr)。b0。end//assign full = full_r。assign rdata = rdata_r。always (posedge rclk )begin rgnext_r = rgnext。 //raddr_r = raddr。編譯文件（testbench）如下所示。// constants // general purpose registers//reg eachvec。reg RD_CLOCK。reg RRESET_N。reg WRESET_N。// wires wire EMPTY_P。wire [7:0] OUT。initial fork WR_CLOCK = 0。 10 WRESET_N = 0。 40 WINC = 0。d10。 RINC = 1。 200 RRESET_N = 1。join always begin 10 WR_CLOCK = ~WR_CLOCK。 end endmoduleB、綜合過程將RTL文件拷如liux系統(tǒng)中進(jìn)行綜合，生成門級網(wǎng)表，并根據(jù)要求來編寫約束文件，使文件最優(yōu)化。 set output delayset_input_delay max 10 clock wclk [get_ports wdata]set_input_delay max 5 clock rclk [get_ports rdata]set_output_delay max clock rclk [get_ports rdata]set_input_delay 5 clock CLOCK [all_inputs]Advanced constrintsgroup_pathset_false_pathset_multicyclepile and write the databasepilewrite hierarchy format verilog output ../rtl/create reportswrite hierarchy format verilog output ../rtl/write_sdc ../rtl/report_timingreport_areareport_area ./report_timing report_constraint all_violators gui_startreportreport_timing結(jié)果系統(tǒng)功能仿真波形：時序仿真波形：總結(jié)及感想雖然該設(shè)計用了差不多兩個星期的時間，雖然效率不高，但也對學(xué)到了不少東西。同時也讓我積累了一些經(jīng)驗，比如在設(shè)計之前還查找相關(guān)的資料，了解該方面設(shè)計目前的大體情況。這樣能在很大程度上提高設(shè)計效率。 input [8:0] wdata。 input winc, wclk, wrst_n, rinc, rclk, rrst_n。 wire N5, N6, \fifomem[0][7] , \fifomem[0][6] , \fifomem[0][5] , \fifomem[0][4] , \fifomem[0][3] , \fifomem[0][2] , \fifomem[0][1] , \fifomem[0][0] , \fifomem[1][7] , \fifomem[1][6] , \fifomem[1][5] , \fifomem[1][4] , \fifomem[1][3] , \fifomem[1][2] , \fifomem[1][1] , \fifomem[1][0] , \fifomem[2][7] , \fifomem[2][6] , \fifomem[2][5] , \fifomem[2][4] , \fifomem[2][3] , \fifomem[2][2] , \fifomem[2][1] , \fifomem[2][0] , \fifomem[3][7] , \fifomem[3][6] , \fifomem[3][5] , \fifomem[3][4] , \fifomem[3][3] , \fifomem[3][2] , \fifomem[3][1] , \fifomem[3][0] , N14, N15, N16, N17, N18, N19, N20, N21, \w2_rptr[2] , full_val, \rbin[2] , empty_val, n10, n20, n23, n26, n29, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, \dp_cluster_0/N34 , N32, \dp_cluster_1/N36 , N31, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193。 wire [2:0] rptr。 wire [1:0] wgnext。 wire [2:0] wbin。 wire [1:0] rbnext_r。 wire [2:0] rbnext。 assign rdata[8] = 139。 FD2 \wptr_reg[2] ( .D(wbnext[2]), .CP(wclk), .CD(wrst_n), .Q(wptr[2]) )。 FD2 \wptr_reg[0] ( .D(wgnext[0]), .CP(wclk), .CD(wrst_n), .Q(wptr[0]) )。 FD2 \r1_wptr_reg[2] ( .D(wptr[2]), .CP(rclk), .CD(rrst_n), .Q(r1_wptr[2]) )。 FD2 \r1_wptr_reg[0] ( .D(wptr[0]), .CP(rclk), .CD(rrst_n), .Q(r1_wptr[0]) )。 FD2 \r2_wptr_reg[1] ( .D(r1_wptr[1]), .CP(rclk), .CD(rrst_n), .QN(n39) )。 FD1 \rbnext_r_reg[2] ( .D(rbnext[2]), .CP(rclk), .Q(rgnext[2]) )。 FD2 \rptr_reg[2] ( .D(rgnext_r[2]), .CP(rclk), .CD(rrst_n), .Q(rptr[2]) )。 FD2 \w2_rptr_reg[2] ( .D(w1_rptr[2]), .CP(wclk), .CD(wrst_n), .Q( \w2_rptr[2] ) )。 FD1 \rbnext_r_reg[1] ( .D(rbnext[1]), .CP(rclk), .Q(rbnext_r[1]) )。 FD1 \rgnext_r_reg[1] ( .D(rgnext[1]), .CP(rclk), .Q(rgnext_r[1]) )。 FD2 \w1_rptr_reg[1] ( .D(rptr[1]), .CP(wclk), .CD(wrst_n), .Q(w1_rptr[1]) )。 FD1 \rbnext_r_reg[0] ( .D(rbnext[0]), .CP(rclk), .Q(rbnext_r[0]) )。 FD1 \rgnext_r_reg[0] ( .D(rgnext[0]), .CP(rclk), .Q(rgnext_r[0]) )。 FD2 \w1_rptr_reg[0] ( .D(rptr[0]), .CP(wclk), .CD(wrst_n), .Q(w1_rptr[0]) )。 FD1 \fifomem_reg[0][7] ( .D(n96), .CP(wclk), .Q(\fifomem[0][7] ), .QN(n73) )。 FD1 \fifomem_reg[0][5] ( .D(n98), .CP(wclk), .Q(\fifomem[0][5] ), .QN(n71) )。 FD1 \fifomem_reg[0][3] ( .D(n100), .CP(wclk), .Q(\fifomem[0][3] ), .QN(n69) )。 FD1 \fifomem_reg[0][1] ( .D(n102), .CP(wclk), .Q(\fifomem[0][1] ), .QN(n67) )。