【正文】 After auto flushing the RX FIFO, the next state depends on the setting. When using the auto flush function, the maximum packet length is 63 bytes in variable packet length mode. Note that when PKTCTRL1APPEND_STATUS is enabled, the maximum allowed packet length is reduced by two bytes in order to make room in the RX FIFO for the two status bytes appended at the end of the packet. Since the entire RX FIFO is flushed when the CRC check fails, the previously received packet must be read out of the FIFO before receiving the current packet. The MCU must not read from the current packet until the CRC has been checked as OK. 4 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet(including the optional address byte). If address recognition is enabled on the receiver, the second byte written to the TX FIFO must be the address byte. If fixed packet length is enabled, the first byte written to the TX FIFO should be the address(assuming the receiver uses address recognition). The modulator will first send the programmed number of preamble bytes. If data is avaible in the TX FIFO, the modulator will send the twobytes(optionally 4byte) 8 sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the plete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has been underflowed will not restart TX mode. If whitening is enabled, everything following the sync words will be whitened. This is done before the optional FEC/interleaver stage. Whitening is enabled by setting =1. If FEC/interleaving is enabled, everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated. FEC is enabled by setting =1. 5 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the synchronism and will receive the first payload byte. If FEC/interleaving is enabled, the FEC decoder will start to decode the first payload byte. The intrerleaver will descramble the bits before any other processing is done to the data. If whitening is enabled, the data will be dewhitened at this stage. When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed number of bytes. Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler putes CRC and matches it with the appended CRC checksum. At the end of the payload, the packet handler will optionally white two extra packet status bytes(see Table27 and Table28) that contain CRC status, link quality indication, and RSSI value. 9 6 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received/transmitted. Additionally, for packets longer than 64 bytes, the RX FIFO needs to be refilled white in TX. This means that the MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX FIFO respectively. There are two possible solutions to get the necessary status information: a) Interrupt Driven Solution The GDO pins can be used in both RX and TX to give an interrupt when a sync word has been received/transmitted or when a plete packet has been received/transmitted by setting =0*06. In addition, there are two configurations for the register that can be