【正文】 壓表的電路設(shè)計(jì)正是用 VHDL 語(yǔ)言完成的， 完成電壓數(shù)據(jù)的采集、轉(zhuǎn)換、處理、顯示 。它支持設(shè)計(jì)庫(kù)和可重復(fù)使用的元件生成，支持階層設(shè)計(jì)，提供模塊設(shè)計(jì)的創(chuàng)建。沈陽(yáng)理工大學(xué)學(xué)士學(xué)位論文 I 摘 要 VHDL(即超高速集成電路硬件描述語(yǔ)言 )是隨著可編程邏輯器件 (PLD)的發(fā)展而發(fā)展起來(lái)的一種硬件描述語(yǔ)言，主要用于描述數(shù)字系統(tǒng)的結(jié)構(gòu)、行為、功能和接口，是電子設(shè)計(jì)自動(dòng)化 (EDA)的關(guān)鍵技術(shù)之一。 它采用一種自上而下 (topdown)的設(shè)計(jì)方法，即從系統(tǒng)總體要求出發(fā)，自上至下地逐步將設(shè)計(jì)內(nèi)容細(xì)化，如劃分為若干子模塊，最后完成系統(tǒng)硬件的整體設(shè)計(jì)。 VHDL 設(shè)計(jì)技術(shù)對(duì)可編程專用集成電路 (ASIC)的發(fā)展起著極為重要的作用。此次設(shè)計(jì)主要應(yīng)用的軟件是美國(guó) ALTERA 公司自行設(shè)計(jì)的一種 Quartus Ⅱ。 關(guān)鍵詞： 電子設(shè)計(jì)自動(dòng)化； VHDL； A/D 采集；數(shù)字電壓表 沈陽(yáng)理工大學(xué)學(xué)士學(xué)位論文 II Abstract VHDL (., ultra high speed integrated circuit hardware description language) is with the development of programmable logic devices (PLD) and developed a kind of hardware description language, is mainly used to describe the structure of the digital system, behavior, function and interface of electronic design automation (EDA) is one of the key technologies. It uses a topdown design method, namely from the overall system requirements, from top to down gradually to refine design content, such as divided into sub modules, finally pleted the overall design of the system hardware. It supports design library and reusable ponents to generate, support the class design, module design creation. VHDL design technology of programmable applicationspecific integrated circuit (ASIC) plays a very important role in the development. The circuit of the design that use VHDL language to plete ,the voltmeter can plete collection of voltage data,conversion,treatment and this time design is primarily the applied software is Quartus Ⅱ . which is made by the United States ALTERA system’s range is 5v to +5v and precision is . Keywords: Electronic Design Automation 。A/D Acquisition digital voltage 沈陽(yáng)理工大學(xué)學(xué)士學(xué)位論文 III 目 錄 1 緒論 ...................................................................................................................................... 1 課題背景和意義 ....................................................................................................... 1 FPGA 設(shè)計(jì)特點(diǎn) ........................................................................................................ 1 FPGA 設(shè)計(jì)流程 ........................................................................................................ 2 硬件描述語(yǔ)言 VHDL ............................................................................................... 3 VHDL 的發(fā)展 ................................................................................................ 3 VHDL 的特點(diǎn) ................................................................................................ 4 VHDL 語(yǔ)言的設(shè)計(jì)流程 ........................................................................................... 5 Quartus II 開(kāi)發(fā)平臺(tái)簡(jiǎn)介 ......................................................................................... 5 Quartus ‖軟件介紹 ......................................................................................... 5 Quartus ‖設(shè)計(jì)輸入 ......................................................................................... 6 文本設(shè)計(jì)輸入方式 .......................................................................................... 6 Quartus II 設(shè)計(jì)仿真 ...................................................................................... 8 2 設(shè)計(jì)任務(wù)與要求 ................................................................................................................ 12 3 設(shè)計(jì)方案 ............................................................................................................................ 13 4 各器件的選擇 .................................................................................................................... 15 A/D 轉(zhuǎn)換器 ADC0809 控制電路 ........................................................................... 15 ADC0809 的功能介紹 ................................................................................. 15 ADC0809 引腳介紹 ..................................................................................... 16 ADC0809 芯片的控制方法及轉(zhuǎn)換過(guò)程 ..................................................... 16 BCD 碼 .................................................................................................................... 18 BCD 碼的介紹 ..................................................................................................... 18 BCD 碼的運(yùn)算 ..................................................................................................... 19 譯碼，顯示電路 ..................................................................................................... 19 5 功能模塊 ............................................................................................................................ 20 ADC0809（ ad） ..................................................................................................... 20 Dataprocess .............................................................................................................. 23 Leddisplay................................................................................................................ 27 頂層模塊設(shè)計(jì) ......................................................................................................... 29 沈陽(yáng)理工大學(xué)學(xué)士學(xué)位論文 IV 結(jié) 論 ........................................................................................................................................ 31 致 謝 ........................................................................................................................................ 32 參考文獻(xiàn) .................................................................................................................................. 33 附錄 A 英文原文 ................................................................................................................... 34 附錄 B 漢語(yǔ)翻譯 ................................................................................................................. 45