中科院研究生院課程vlsi測試與可測試性設(shè)計-文庫吧資料
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【正文】 ased ATPG ? ATPG for Delay and Bridge Faults ? Other Topics in Test Generation ? Concluding Remarks EE141 VLSI Test Principles and Architectures Test Generation 5 5 Introduction ? Test generation is the breadandbutter in VLSI Testing ? Efficient and powerful ATPG can alleviate high costs of DFT ? Goal: generation of a small set of effective vectors at a low putational cost ? ATPG is a very challenging task ? Exponential plexity ? Circuit sizes continue to increase (Moore’s Law) – Aggravate the plexity problem further ? Higher clock frequencies – Need to test for both structural and delay defects EE141 VLSI Test Principles and Architectures Test Generation 6 6 Conceptual View of ATPG ? Generate an input vector that can distinguish the defectfree circuit from the hypothetically defective one EE141 VLSI Test Principles and Architectures Test Generation 7 7 Fault Models ? Instead of targeting specific defects, fault models are used to capture the logical effect of the underlying defect ? Fault models considered in this chapter: ? Stuckat fault ? Bridging fault ? Transition fault ? Pathdelay fault EE141 VLSI Test Principles and Architectures Test Generation 8 8 Simple illustration of ATPG ? Consider the fault d/1 in the defective circuit ? Need to distinguish the output of the defective circuit from the defectfree circuit ? Need: set d=0 in the defectfree circuit ? Need: propagate effect of fault to output ? Vector: abc=001 (output = 0/1) EE141 VLSI Test Principles and Architectures Test Generation 9 9 Example 1 a b c d e f 1 0 g h i 1 sa0 j k z 0(1) 1(0) 1 Test vector for h sa0 fault Good circuit value Faulty circuit value EE141 VLSI Test Principles and Architectures Test Generation 10 10 A Typical ATPG System ? Given a circuit and a fault model ? Repeat ? Generate a test for each undetected fault ? Drop all other faults detected by the test using a fault simulator ? Until all faults have been considered ? Note 1: a fault may be untestable, in which no test would be generated ? Note 2: an ATPG may abort on a fault if the resources needed exceed a preset limit EE141 VLSI Test Principles and Architectures Test Generation 11 11 Category of ATPG ? Simulationbased ? Exhaustive ? Randompattern generation ? Pseudorandompattern generation ? Path sensitization ? Dalgorithm, 9V algorithm ? PODEM, FAN ? TOPS, SOCRATES ? Boolean satisfiability amp。 Neural work ? Boolean difference ? Boolean satisfiability (2SAT, 3SAT) ? Neural work EE141 VLSI Test Principles and Architectures Test Generation 12 12 Random Test Generation ? Simplest form of test generation ? N tests are randomly generated ? Level of confidence on random test set T ? The probability that T can detect all stuckat faults in the given circuit ? Quality of a random test set highly depends on the underlying circuit ? Some circuits have many randomresistant faults EE141 VLSI Test Principles and Architectures Test Generation 13 13 Weighted Random Test Generation ? Bias input probabilities to target random resistant faults ? Consider an 8input AND gate ? Without biasing input probabilities, the prob of generating a logic 1 at the gate output = ()8 = ? If we bias the inputs to , then the prob of generating a logic 1 at the gate output = ()8 = ? Obtaining an optimal set of input probabilities a difficult task ? Goal: increase the signal probabilities of hardtotest regions EE141 VLSI Test Principles and Architectures Test Generation 14 14 Exhaustive Test Generation ? Exhaustive Test
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