中科院研究生院課程vlsi測試與可測試性設(shè)計-展示頁
2024-10-28 09:14本頁面
【正文】 ing ? Apply 2n patterns to an ninput binational circuit under test (CUT) ? Guarantees all detectable faults in the binational circuits are detected ? Test time maybe be prohibitively long if the number of inputs is large ? Feasible only for small circuits ? Pseudoexhaustive Testing ? Partition circuit into respective cones ? Apply exhaustive testing only to each cone ? Still guarantees to detect every detectable fault based on Lemma 1 EE141 VLSI Test Principles and Architectures Test Generation 15 15 Path Sensitization Method Circuit Example 1 Fault Sensitization 2 Fault Propagation 3 Line Justification EE141 VLSI Test Principles and Architectures Test Generation 16 16 Path Sensitization Method Circuit Example ? Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 0 D D 1 1 1 D D D EE141 VLSI Test Principles and Architectures Test Generation 17 17 ? Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because Dfrontier (chain of D or D) disappears 1 D D D D D 1 1 Path Sensitization Method Circuit Example EE141 VLSI Test Principles and Architectures Test Generation 18 18 ? Final try: path g – i – j – k – L – test found! 0 D D D 1 D D 1 0 1 Path Sensitization Method Circuit Example EE141 VLSI Test Principles and Architectures Test Generation 19 19 History of Algorithm Speedups A lgo rit hmD A LGPOD EMFA NTOPSSOC R A TESWa icu ka us ki et al.ESTTR A NR ec ur s iv e le ar nin gTafe rt s ho fer et al.Es t. s pe ed up ov er D A LG(no rm alize d t o D A LG tim e)172329215 74 A TPG Sy s te m21 89 A TPG Sy s te m87 65 A TPG Sy s te m30 05 A TPG Sy s te m48525057Y ea r1966198119831987198819901991199319951997????EE141 VLSI Test Principles and Architectures Test Generation 20 20 Roth’s 5Valued and Muth’s 9Valued Sym b o lDD01XG0G1F0F1M e a n in g1 /00 /10 /01 /1X /X0 /X1 /XX /0X /1F a ilin gM a c h in e1001XXX01Go o dM a c h in e 0101X01XXR o th ’sA lg e b raM u th ’sA d d it io n s1 1 0 0 EE141 VLSI Test Principles and Architectures Test Generation 21 21 Forward Implication ? Results in logic gate inputs that are significantly labeled so that output is uniquely determined ? AND gate forward implication table: EE141 VLSI Test Principles and Architectures Test Generation 22 22 Backward Implication ? Unique determination of all gate inputs when the gate output and some of the inputs are given EE141 VLSI Test Principles and Architectures Test Generation 23 23 Example 2 Fault A sa0 ?Step 1 – DDrive – Set A = 1 D 1 D EE141 VLSI Test Principles and Architectures Test Generation 24 24 Step 2 Example 2 ?Step 2 – DDrive – Set f = 0 D 1 0 D D EE141 VLSI Test Principles and Architectures Test Generation 25 25 Step 3 Example 2 ?Step 3 – DDrive – Set k = 1 D 1 0 D D 1 D EE141 VLSI Test Principles and Architectures Test Generation 26 26 Step 4 Example 2 ?Step 4 – Consistency – Set g = 1 D 1 0 D D 1 D 1 EE141 VLSI Test Principles and Architectures Test Generation 27 27 Step 5 Example 2 ?Step 5 – Consistency – Set f = 0 D 1 0 D D 1 D 1 EE141 VLSI Test Principles and Architectures Test Generation 28 28 Step 6 Example 2 ?Step 6 – Consistency – Set c = 0, Set e = 0 D 1 0 D D 1 D 1 0 0 EE141 VLSI Test Principles and Architectures Test Generation 29 29 Test found Example 2 ?Step 7 – Consis
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