數(shù)字信號外文翻譯--基于fpga的cordic算法綜述-文庫吧資料
2025-05-22 01:48本頁面
【正文】 ion from the CORDIC equations. From there, we will look at a minimum hardware solution and a maximum performance solution. 5. CONCLUSIONS The CORDIC algorithms presented in this paper are well known in the research and superputing circles. It is, however, my experience that the majority of today39。x d x?? 39。y d x?? 39。π/2. This gives the correction iteration: 39。 c o s [ ta n ]y y x? ? So far, nothing is simplified. However, if the rotation angles are restricted so that tan 2 i? ??? , the multiplication by the tangent term is reduced to simple shift operation. Arbitrary angles of rotation are obtainable by performing a series of successively smaller elementary rotations. If the decision at each iteration, i, is which direction to rotate rather than whether or not to rotate, then the cos( )i? term bees a iterative rotation can now be expressed as: 1 [ 2 ]ii i i i ix k x y d ?? ? ? ? ? 1 ii i i i iy y x ?? ? ? ? Where: 21/ 1 2 iik ??? 1id?? Removing the scale constant from the iterative equations yields a shiftadd algorithm for vector rotation. The product of the Ki39。 co s siny y x?? which rotates a vector in a Cartesian plane by the angle φ These can be rearranged so that: 39。A survey of CORDIC algorithms for FPGA based puters 1. ABSTRACT The current trend back toward hardware intensive signal processing has uncovered a relative lack of understanding of hardware signal processing architectures. Many hardware efficient algorithms exist, but these are generally not well known due to the dominance of software systems over the past quarter century. Among these algorithms is a set of shiftadd algorithms collectively known as CORDIC for puting a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. While there are numerous articles covering various aspects of CORDIC algorithms, very few survey more than one or two, and even fewer concentrate on implementation in FPGAs. This paper attempts to survey monly used functions that may be acplished using a CORDIC architecture, explain how the algorithms work, and explore implementation specific to FPGAs. 2. INTRODUCTION The digital signal processing landscape has long been dominated by microprocessors with enhancements such as single cycle multiplyaccumulate instructions and special addressing modes. While these processors are low cost and offer extreme flexiblility, they are often not fast enough for truly demanding DSP tasks. The advent of reconfigurable logic puters permits the higher speeds of dedicate
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