【正文】 tools that can generate structures for monly used algorithms. A hardware piler for parametrised DCTbased applications is ready, and we are creating similar pilers for other important algorithms.4 . Ideally, a high level synthesis interactive tool could be developed that will use libraries of “hardware pilers”. Such a tool should be able to read the functional description of a DSP algorithm and map it on one or more .6. EXAMPLE AN 8 POINT .The Discrete Cosine Transform [51[6] has been widely used in DSP algorithms. Recently, this transformation has been used in many image pression standards like JPEG, MPEG and . It’s represented by the following equation:y = J Z E , . x (2)For the efficient putation of DCT, H. C. Karathanasis [7] has recently proposed the following structure. Thistopology putes the one dimensional 8point DCT and can be used (with minimal changes) for the putation of IDCT, DST and the two dimensional 8x8 DCT. The Rotations shown on the flow diagram can be implemented with CORDIC iterations [8]. Taking into advantage the fact that the rotation angles are predefined we can map those rotations directly on the CORDIC array of the DSP Board. The two rotators of 3d36 are implemented by the same group of elements in the array in order to achieve maximum hardware utilisation.The Butterfly structures and the addershbtractors of the DCT flowchart have been implemented on the FPGA. The adders are bit serial with 12 bits accuracy and require only one CLB to be implemented. Figure 6, shows a simplified schematic diagram of these structures. The performance of the proposed DCT implementation is determined by the performance of the FPGA. This structure has been designed and simulated using high level languages (VHDL and C) assuming a clock speed of about 50 MHz for the structures built in the FPGA, which is a reasonable speed due to 。 each element contains two pairs of adderdsubtractors, one for the putation of theCORDIC iterations, and the other for the proper scaling of the resulting vector. The structure of one processing element is shown in figure 2. The shifters of each pair are controlled by a 4 bit shift value. The SC (Shift value Select) signal is controlled by the FPGA and determines which set of shift values will be used. These values are loaded to the CORDIC array during the board reconfiguration phase and can be used when we want to map a large sequence of different operations (. different rotation angles) on one processing element. The operation mode of each adderlsubtractor is controlled directly by the FPGA, via the Su and Sd signals. These signals together with SC control the whole functionality of the CORDIC processing element.The array39。 m=O is for Multiplication and Division, m=l is for Circular Rotation and Vectoring and m=1 for Hyperbolic Rotation and Vectoring. Since equations (1) scalie the results by a predefined factor s number of extra scaling Iterations have to be applied. In its original formulation, parameter pi is allowed to have only two values, +1 and 1 . If we allow pi to have the value 0, then we can omit those iterations for which pi is 0, thus saving a considerable amount of hardware [8] . This cannot be acplished with a conventional CORDIC processor, because the shift values (ij) are fixed, in the sense that they are hardwired. In the proposed system however, the reconfigurability offered by the FPGA allows us to use this variation of the algorithm. The functions directly supported by the CORDIC architecture include Circular and Hyperbolic Rotation and Vectoring, Multiplication and Division. Furthermore, with some additional circuitry one can also pute other functions like square root, exponentials, logarithms, etc. [IO] This set of functions covers most DSP algorithms. Moreover, by making minor changes to some algorithms, one can take advantage of CORDIC39。p 239。參考文獻(xiàn)1 . 2 FoxPro課程設(shè)計案例精. 3 FoxPro高級應(yīng)用實(shí)例. 4 . 清華大學(xué)出版社. 1998. 6 7 8 DATE C Introduction to Database Systems ,AddisonWesley,version 6 ,19959 Database Language SQL ,1993 10 周恒 .數(shù)據(jù)開發(fā)關(guān)鍵技術(shù)與實(shí)例應(yīng)用. 11 FoxPro程序設(shè)計基礎(chǔ). 12 范例入門與提高 . 13 FoxPro 附錄A 外文翻譯A Reconfigurable DSP BoardBased on CORDIC ElementsE. P. Mariatos, M. K. Birbas* and A. N. Birbas**VLSI Design Lab. University of Patras, Greece* Synergy Systems, 68 Amerikis AV. Patras, Greece**Applied Electronics Lab. University of Patras, GreeceABSTRACTIn this paper, a reconf igurable rapid prototyping system,oriented to DSP applications is proposed. Using the novel approach of bining the reconfigurability offered by an FPGA unit and the processing power of the CORDIC architecture, a fast, flexible, scalable and highly parallel structure has been developed. The results obtained by experimenting with the implementation of DCT algorithms are really promising, in terms of performance and versatility, which allows us to proceed for the development of a prototype that will be targeted to an image pression standard like . Moreover, it is envisioned to built a parametrised library of hardware pilers that will map a wide range of DSP algorithms on the proposed board.1. INTRODUCTIONMost algorithms that are used in multimedia and other DSP systems, need hardware that can operate at very high speeds that conventional DSP processors cannot achieve. The use of application specific hardware offers the desired performance, however the penalty in terms of time to market and development cost is very high. Consequently, a lowcost rapid prototyping system, would provide an efficient solution to the above dilemma.Most rapid prototyping boards are general purpose in the sense that they are designed to support diverse application areas. This leads to expensive systems with poor hardware utilisation. Furthermore