【正文】 認(rèn)無誤后，返回“證書打印”表單。在整個開發(fā)制作過程中得到了院系及輔導(dǎo)教師的大力支持，特別感謝陳紅老師的辛勤輔導(dǎo)與全力支持。s structure is shown in figure 3.Emphasis should be posed to the extra input and output channels that can break the array in more, smaller arrays, operating in parallel, via the simple multiplexing circuitryshown in figure 3. It should also be mentioned, that the array has only local data exchange and all elements are equivalent. This guarantees that there is no bottleneck in the process of mapping an algorithm on this array. Indeed, the only signals that specify this mapping are GC () and GS ().The interfacing of the CORDIC array to the system is acplished through the FPGA unit. More specifically, the FPGA module controls the behaviour of the array and of all the I/O channels. We chose to use serialmunications for the input/output of data, so that we can reduce significantly the number of pins needed. The number of elements that will be contained in the chip has to be a promise between speed, hardware utilisation, functionality and the number of pins. We can set a limit to the pin number, if we take into account the FPGA chips that are currently available and the cost of the IC which we want to fabricate. This limit was set to 120 for the board we are developing, but a number of 200 is also feasible. On the other hand, if a key factor is the reduction of cost, a solution with only 80 pins can be acceptable, with a considerable loss of speed for many applications.Based on the above discussion we chose to design a CORDIC array with 16 elements and 4 extra data YO channels. Our experience has shown that 16 elements are enough for most DSP applications like image pression and hifi audio. Moreover, due to the scalability of the wle system, two or more boards can be cascaded if the designer wants to implement more plex algorithms that require higher accuracy and speed. The CORDIC array is currently under design using standard cells. A first version using FPGAs has been developed. A prototype of the DSP board using this FPGA implementation is under development and teshoting.4. THE FPGAIn the proposed DSP board, the role of the FPGA is to configure appropriately the CORDIC array for the associated algorithm. This is acplished by controlling the connections which program each of the CORDIC elements to the desired function mode, and by implementing in the FPGA simple operations which plement the main calculations carried out by the CORDIC array. Through the reconfigurability of the FPGA, the enduser can view the whole system as a set of CORDIC elements that can be connected in various topologies to perform an unlimited set of algorithms.The I/O pins of the FPGA can be divided in three sets, according to their usage. First, there are the data input/output pins that carry signals in and out of the board, municating with the host system. Second, there are the CORDIC control pins, which are used to determine the operation of the elements in the CORDIC array. Finally, the CORDIC X,Y and extra data channels, are pins who are used for data exchange between the FPGA and the CORDIC array. The FPGA that is used, must be able to fulfil two requirements. It must have a relatively large number of logic blocks, so that the all the required structures can be configured on one chip, and it must have enough speed to be able to carry out operations as fast as the algorithms demand. Furthermore, it has to be fully reconfigurable, since it is going to be reprogrammed very frequently on board. For those reasons the XILINX family has been chosen and specifically XC3090 which has 144 user 110pins and contains 320 Configurable Logic blocks (CLBs) [9].5. RECONFIGURATION OF THE BOARDThe board will be connected to a host system which loads the configuration on a RAM chip. The FPGA reads the bit stream directly from the RAM. This approach has the versatility provided by the fact that the FPGA is directly interfaced through the host system’s console, and alsoavoids the slow process of programming the FPGA through the host’s I/O channels.1 . Tools provided by the FPGA manufacturer. They are schematic capture, simulation and verification tools, and a program that generates the required bit stream2 . Programs that can create the netlist description from a higher level mapping of the algorithm on the board. We are currently developing such a tool.3 . “Algorithm Specific Hardware Compilers“。并編寫了《考務(wù)管理系統(tǒng)》使用說明書（詳見系統(tǒng)光盤及軟件說明書），以供用戶測試使用。 8. 數(shù)據(jù)錄入：點擊按鈕“錄入”出現(xiàn)子菜單“統(tǒng)計錄入”，“成績錄入”，“證書錄入”，點擊后出現(xiàn)相應(yīng)的錄入界面，可以進行添加、刪除、修改等操作。如果您需要查詢具體的信息，則可以點擊“搜索”，輸入學(xué)校名稱，然后點擊“查詢”就可以查詢到您所需要的報名信息，如不需要，則點擊“退出”就可以退出該查詢系統(tǒng)。添加完內(nèi)容表后可以進行保存、編譯、測試幫助文件。錄入模塊界面如圖413所示。用戶可以通過選擇考核點的信息來具體查看考場信息。（7）“證書”主要調(diào)用了證書模塊的界面，可以完成證書所需要各種功能。(8) 系統(tǒng)維護模塊：主要功能：操作員管理；口令管理；數(shù)據(jù)庫管理。七個子模塊名稱分別為：報名模塊，匯總上報、考場編排、成績接收、成績統(tǒng)計、證書管理和系統(tǒng)維護。(3) 用戶對考生的信息進行匯總上報，生成上報盤，然后進行考場的編排。其轉(zhuǎn)換原則為：首先每個實體轉(zhuǎn)化為一個關(guān)系，有屬性的聯(lián)系也應(yīng)轉(zhuǎn)化為一個關(guān)系，然后需要給出每個關(guān)系的關(guān)鍵字。數(shù)據(jù)流圖共有四種符號：矩形表示數(shù)據(jù)的源點或終點，圓或橢圓表示數(shù)據(jù)存儲，箭頭表示數(shù)據(jù)流，即特定數(shù)據(jù)的流動方向，根據(jù)現(xiàn)行考務(wù)管理系統(tǒng)的業(yè)務(wù)流程，售前確定數(shù)據(jù)流圖中的源點和終點都選為考生，如此得到了考務(wù)管理系統(tǒng)的基本系統(tǒng)模型如圖33所示。從報名、編排考場、閱卷、統(tǒng)計成績直至發(fā)放合格證書，環(huán)節(jié)多，工作量大，采用原有的人工管理方式，必然周期長，效率低，不能適應(yīng)現(xiàn)行工作的要求。另外，管理人員發(fā)生更迭時，因為交接手續(xù)不完善，考務(wù)管理工作就會陷于困境。 可以創(chuàng)建查詢搜索那些滿足指定條件的記錄，也可以根據(jù)需要對這些記錄排序和分組，并根據(jù)查詢結(jié)果創(chuàng)建報表、表及圖形。 數(shù)據(jù)庫管理系統(tǒng)的軟件產(chǎn)品。該系統(tǒng)軟件命名為：考務(wù)管理系統(tǒng)。 開發(fā)背景 現(xiàn)代計算機科學(xué)迅猛發(fā)展，計算機在現(xiàn)代管理中處于非常重要的地位。成績接收：能接收下發(fā)的成績數(shù)據(jù)盤，打印出成績單、成績冊。 Visual FoxPro作為一個數(shù)據(jù)庫管理系統(tǒng)的數(shù)據(jù)庫開發(fā)工具，不僅具有數(shù)據(jù)庫管理系統(tǒng)的功能，而且提供大量的命令和函數(shù)以及面向?qū)ο蟮木幊趟枷胪瓿捎脩艚缑妗?shù)據(jù)報表等數(shù)據(jù)處理能力，特別適應(yīng)于一般企業(yè)和部門的信息管理系統(tǒng)的應(yīng)用開發(fā)。首先報名的基本信息只能通過考務(wù)人員的手工操作記錄到報名冊中，然后依據(jù)報名冊上報給市考核辦進行匯總、進行考場編排。 系統(tǒng)在功能完整的同時，應(yīng)具有很好的可靠性。根據(jù)以上總結(jié)，得出其現(xiàn)行的業(yè)務(wù)流圖為：報名表報名冊 報名盤 匯總名冊 上報盤 考場表 準(zhǔn)考證 考場庫考場編排報 名匯總上報報圖31 考前處理業(yè)務(wù)流圖說明：按報名點輸入、修改報名表，并能查詢、打印報名冊，生成各報名點的報名庫。通常實體用矩形來表示，屬性用橢圓或圓矩形來表示，聯(lián)系用菱形來表示。按照第三范式的要求對比以上各個關(guān)系，在所有關(guān)系中都不存在非主屬性對關(guān)鍵字的部分依賴，即滿足第三范式。根據(jù)數(shù)據(jù)分析階段建立的概念模型，已經(jīng)得出滿足第三范式的若干個關(guān)系描述，該階段的主要工作就是把前一階段的成果轉(zhuǎn)化為具體的數(shù)據(jù)庫。具體來說就是把經(jīng)過總體設(shè)計得到的各個模塊詳細(xì)的加以描述。主菜單的實現(xiàn)主要是通過VF提供的菜單編輯器來實現(xiàn)。各代理點的信息可以通過手動修改，與報名點連接的是院系的選擇，可以將各報考點的信息細(xì)分，最后為個報名點的具體報考人員的信息。打印調(diào)用了打印報表程序，可進行打印預(yù)覽。本系統(tǒng)將建立HTML樣式的幫助文件，包括應(yīng)用系統(tǒng)各個模塊的功能介紹和幫助主題等內(nèi)容，是一種基于HTML文件特征的CHM幫助文件。安裝