【正文】 匯總名冊 上報盤 考場表 準(zhǔn)考證 考場庫考場編排報 名匯總上報報圖31 考前處理業(yè)務(wù)流圖說明：按報名點輸入、修改報名表，并能查詢、打印報名冊，生成各報名點的報名庫。同時也不利于推廣計算機應(yīng)用。 系統(tǒng)在功能完整的同時，應(yīng)具有很好的可靠性。 系統(tǒng)功能需求分析鑒于考務(wù)管理的現(xiàn)狀，要從根本上解決存在的問題，必須對整個管理組織模式進行調(diào)整，運用一套更合理、更完善的考務(wù)管理系統(tǒng)來對其業(yè)務(wù)過程的各個環(huán)節(jié)進行更加科學(xué)、有力的管理。首先報名的基本信息只能通過考務(wù)人員的手工操作記錄到報名冊中，然后依據(jù)報名冊上報給市考核辦進行匯總、進行考場編排。使用視圖，可以從一個或多個相關(guān)聯(lián)的表中，按一定條件抽取一系列數(shù)據(jù)，并可以通過視圖更新這些表中的數(shù)據(jù), 還可以使用視圖從網(wǎng)上取得數(shù)據(jù)，從而收集或修改遠程數(shù)據(jù)。 Visual FoxPro作為一個數(shù)據(jù)庫管理系統(tǒng)的數(shù)據(jù)庫開發(fā)工具，不僅具有數(shù)據(jù)庫管理系統(tǒng)的功能，而且提供大量的命令和函數(shù)以及面向?qū)ο蟮木幊趟枷胪瓿捎脩艚缑?、?shù)據(jù)報表等數(shù)據(jù)處理能力，特別適應(yīng)于一般企業(yè)和部門的信息管理系統(tǒng)的應(yīng)用開發(fā)。這些軟件主要分為兩種：一類屬于大型數(shù)據(jù)庫管理系統(tǒng)，另一類屬于小型數(shù)據(jù)庫管理系統(tǒng)。成績接收：能接收下發(fā)的成績數(shù)據(jù)盤，打印出成績單、成績冊。主要利用面向?qū)ο缶幊碳夹g(shù)采用Visual For Pro 數(shù)據(jù)庫開發(fā)軟件制作。 開發(fā)背景 現(xiàn)代計算機科學(xué)迅猛發(fā)展，計算機在現(xiàn)代管理中處于非常重要的地位。因此，適合普通高?？紕?wù)需求，高效、合理、科學(xué)編排體制，具有友好便捷的操作、打印及查詢的界面的考務(wù)管理系統(tǒng)軟件將得到認可及廣泛應(yīng)用，并具有良好的市場前景。該系統(tǒng)軟件命名為：考務(wù)管理系統(tǒng)。能打印準(zhǔn)考證和各種考務(wù)表格。 數(shù)據(jù)庫管理系統(tǒng)的軟件產(chǎn)品。Visual FoxPro是用來建立關(guān)系型數(shù)據(jù)庫應(yīng)用程序的一種功能強大的工具。 可以創(chuàng)建查詢搜索那些滿足指定條件的記錄，也可以根據(jù)需要對這些記錄排序和分組，并根據(jù)查詢結(jié)果創(chuàng)建報表、表及圖形?？紕?wù)人員完全依靠手工建立姓名、學(xué)號等對學(xué)生的基本信息進行登記報名。另外，管理人員發(fā)生更迭時，因為交接手續(xù)不完善，考務(wù)管理工作就會陷于困境。作為陜西省的一個組成部分，本系統(tǒng)必須具有良好的開放性，既要滿足現(xiàn)有集成需求，又要為將來系統(tǒng)的擴展預(yù)留接口。從報名、編排考場、閱卷、統(tǒng)計成績直至發(fā)放合格證書，環(huán)節(jié)多，工作量大，采用原有的人工管理方式，必然周期長，效率低，不能適應(yīng)現(xiàn)行工作的要求?？己蠊ぷ髦饕獮椋撼煽兘邮?、成績統(tǒng)計、數(shù)據(jù)錄入、證書管理及系統(tǒng)維護等工作。數(shù)據(jù)流圖共有四種符號：矩形表示數(shù)據(jù)的源點或終點，圓或橢圓表示數(shù)據(jù)存儲，箭頭表示數(shù)據(jù)流，即特定數(shù)據(jù)的流動方向，根據(jù)現(xiàn)行考務(wù)管理系統(tǒng)的業(yè)務(wù)流程，售前確定數(shù)據(jù)流圖中的源點和終點都選為考生，如此得到了考務(wù)管理系統(tǒng)的基本系統(tǒng)模型如圖33所示。圖中共有三種符號：實體、屬性和聯(lián)系。其轉(zhuǎn)換原則為：首先每個實體轉(zhuǎn)化為一個關(guān)系，有屬性的聯(lián)系也應(yīng)轉(zhuǎn)化為一個關(guān)系，然后需要給出每個關(guān)系的關(guān)鍵字。在得出以上關(guān)系后，根據(jù)關(guān)系數(shù)據(jù)庫的理論要求，需要對所有關(guān)系進行關(guān)系規(guī)范化，至少要求各個關(guān)系達到第三范式的要求。(3) 用戶對考生的信息進行匯總上報，生成上報盤，然后進行考場的編排。由此給出考務(wù)管理系統(tǒng)的系統(tǒng)功能結(jié)構(gòu)圖，如圖42所示：報名系統(tǒng)匯總上報考場編排成績接收成績統(tǒng)計證書管理系統(tǒng)維護主控模塊圖42 考務(wù)管理系統(tǒng)的系統(tǒng)功能結(jié)構(gòu)圖在需求分析階段已完成了系統(tǒng)的數(shù)據(jù)的分析。七個子模塊名稱分別為：報名模塊，匯總上報、考場編排、成績接收、成績統(tǒng)計、證書管理和系統(tǒng)維護。 詳細設(shè)計階段的根本任務(wù)是確定應(yīng)該怎樣具體實現(xiàn)所要求的系統(tǒng)，也就是經(jīng)過這個階段的實際工作，應(yīng)該得出對目標(biāo)系統(tǒng)的精確描述，從而在系統(tǒng)實現(xiàn)階段可以把這個描述直接翻譯成用某種程序設(shè)計語言書寫的程序。(8) 系統(tǒng)維護模塊：主要功能：操作員管理；口令管理；數(shù)據(jù)庫管理。 圖48 登陸界面 主菜單的功能程序運行后系統(tǒng)菜單顯示于主程序界面頂部，主要用于用戶選擇調(diào)用相應(yīng)的數(shù)據(jù)及程序操作。（7）“證書”主要調(diào)用了證書模塊的界面，可以完成證書所需要各種功能。其中錄入了西安的各大高校和部分雙考的代理點。用戶可以通過選擇考核點的信息來具體查看考場信息。底部按鈕可以分別實現(xiàn)其相應(yīng)的功能。錄入模塊界面如圖413所示。 圖414 證書模塊界面 幫助文件的設(shè)計 在Visual （即HTML樣式）的幫助系統(tǒng)，HTML樣式的幫助文件可以由HTML Help WorkShop 創(chuàng)建。添加完內(nèi)容表后可以進行保存、編譯、測試幫助文件。 應(yīng)用系統(tǒng)安裝1．使用安裝盤：本應(yīng)用系統(tǒng)經(jīng)過Visual ，使用時只須按標(biāo)號順序在Windows環(huán)境下直接安裝即可。如果您需要查詢具體的信息，則可以點擊“搜索”，輸入學(xué)校名稱，然后點擊“查詢”就可以查詢到您所需要的報名信息，如不需要，則點擊“退出”就可以退出該查詢系統(tǒng)。任意選擇考核點中的一個信息，科目欄里的外語或者計算機，選擇需要的等級，點擊“自動編排”按鈕，系統(tǒng)將自動更新現(xiàn)有的考場庫進行考場的編排，這時就可以點擊“打印準(zhǔn)考證”按鈕打印。 8. 數(shù)據(jù)錄入：點擊按鈕“錄入”出現(xiàn)子菜單“統(tǒng)計錄入”，“成績錄入”，“證書錄入”，點擊后出現(xiàn)相應(yīng)的錄入界面，可以進行添加、刪除、修改等操作。11．幫助：點擊按鈕“幫助”出現(xiàn)子菜單“目錄與索引”，“關(guān)于”。并編寫了《考務(wù)管理系統(tǒng)》使用說明書（詳見系統(tǒng)光盤及軟件說明書），以供用戶測試使用。最后再次對所有關(guān)心我，幫助我的老師及同學(xué)表以深切的感謝。s structure is shown in figure 3.Emphasis should be posed to the extra input and output channels that can break the array in more, smaller arrays, operating in parallel, via the simple multiplexing circuitryshown in figure 3. It should also be mentioned, that the array has only local data exchange and all elements are equivalent. This guarantees that there is no bottleneck in the process of mapping an algorithm on this array. Indeed, the only signals that specify this mapping are GC () and GS ().The interfacing of the CORDIC array to the system is acplished through the FPGA unit. More specifically, the FPGA module controls the behaviour of the array and of all the I/O channels. We chose to use serialmunications for the input/output of data, so that we can reduce significantly the number of pins needed. The number of elements that will be contained in the chip has to be a promise between speed, hardware utilisation, functionality and the number of pins. We can set a limit to the pin number, if we take into account the FPGA chips that are currently available and the cost of the IC which we want to fabricate. This limit was set to 120 for the board we are developing, but a number of 200 is also feasible. On the other hand, if a key factor is the reduction of cost, a solution with only 80 pins can be acceptable, with a considerable loss of speed for many applications.Based on the above discussion we chose to design a CORDIC array with 16 elements and 4 extra data YO channels. Our experience has shown that 16 elements are enough for most DSP applications like image pression and hifi audio. Moreover, due to the scalability of the wle system, two or more boards can be cascaded if the designer wants to implement more plex algorithms that require higher accuracy and speed. The CORDIC array is currently under design using standard cells. A first version using FPGAs has been developed. A prototype of the DSP board using this FPGA implementation is under development and teshoting.4. THE FPGAIn the proposed DSP board, the role of the FPGA is to configure appropriately the CORDIC array for the associated algorithm. This is acplished by controlling the connections which program each of the CORDIC elements to the desired function mode, and by implementing in the FPGA simple operations which plement the main calculations carried out by the CORDIC array. Through the reconfigurability of the FPGA, the enduser can view the whole system as a set of CORDIC elements that can be connected in various topologies to perform an unlimited set of algorithms.The I/O pins of the FPGA can be divided in three sets, according to their usage. First, there are the data input/output pins that carry signals in and out of the board, municating with the host system. Second, there are the CORDIC control pins, which are used to determine the operation of the elements in the CORDIC array. Finally, the CORDIC X,Y and extra data channels, are pins who are used for data exchange between the FPGA and the CORDIC array. The FPGA that is used, must be able to fulfil two requirements. It must have a relatively large number of logic blocks, so that the all the required structures can be configured on one chip, and it must have enough speed to be able to carry out operations as fast as the algorithms demand. Furthermore, it has to be fully reconfigurable, since it is going to be reprogrammed very frequently on board. For those reasons the XILINX family has been chosen and specifically XC3090 which