高速數(shù)字電路設(shè)計及emc設(shè)計(參考版)
2025-07-03 16:29本頁面
【正文】 Do not split or gap the return plane under any connector.216。 Keep all clock lines as short as possible.216。 Use logic families that are no faster than necessary.216。 The circuit board signal return needs a HF (MHz) connection to any surrounding metal chassis at the connector to reduce VCM applied to the cable.216。 Do not allow any traces to cross any gaps in the return plane.216。 Keep all metal structures at the same RF voltage.216。 Unintended sharp transitions in signal level may indicate reflections due to impedance mismatches.216。 A trace may need to be treated as a transmission line when trace length λ/20, or propagation delay (pulse rise time)/4.216。 Connect all metal fill areas to the return plane.216。 Connect “guard traces” to the return plane on both ends so that the traces can serve as additional signal return paths.216。 Unintended sharp transitions in signal level may indicate reflections due to impedance mismatches.216。 Ringing may indicate excessive wiring inductance.216。 Self shielding occurs when the return current is allowed to surround the outgoing current, as in a coaxial cable.216。 A small loop area is more important than short trace lengths.216。 The return (ground) plane may require gaps to control the path of kHz currents. Do not use gaps to control the flow of MHz currents.216。 All critical signals (DC power, high frequency, large amplitude or small amplitude) need a closely located return path. Prefer signal and return traces ” apart.216。 For boards with power and return planes, the integrated circuits share all the decoupling capacitors on the board. Routing of Signal Output and Return Paths216。 Minimize the series inductance of any lumped decoupling capacitors. For boards with power and return planes, this inductance is caused by the traces and vias that connect the capacitor to the planes.216。 Do not allow different DC voltage planes to overlap one another. For example the +5V and +15V planes should not overlap. Bipolar DC voltage planes, such as +15V and –15V, should overlap.216。 Provide space for shunt capacitors on all I/O lines.216。 Keep MHz circuits away from connectors. Do not allow MHz circuits to be located between connectors.216。 Components using multiple DC voltages must straddle the boundary between the different voltage areas.216。 Laterally segregate ponents based on the DC voltage that they use.216。 Let the circuit board layout dictate the connector pin location and function assignment.216。Where should shield be connected? On side of RF source opposite cable. 電路板EMC準則總結(jié) Component Placement216。 radiated emission amp。15) to overlap.②Components using multiple DC voltages () must straddle the boundary between different voltage areas.③Keep all connectors on the same edge of the board.Can low level and high level circuits share a mon current return plane?Yes, but their currents and magnetic fields must not overlap.對f10kHz，將低電流和高電流的回流通道隔開。⑤on the surface of the circuit board.PCB DC power bus decoupling frequency and path of various currents: How to distribute DC power from a single supply to both analog and digital circuits?1. use only low impedance bus?(one power and one return plane).2. use two separate low impedance buses? (two power and two return planes)3. use one shared return plane and two separate +VDC distribution planes or traces? 元件放置與信號層分配模擬、數(shù)字混合PCB布局元件布放原則：①Laterally segregate ponents by the DC Voltage they use. Do not allow different DC voltage planes(+5 amp。④built into the DC power amp。②inside the IC package。 Z0≈10Ω, bad。 通過濾波減小直流電源噪聲EMC for a PCB is most affected by the Z0 of the DC power bus.
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