高速數(shù)字電路設(shè)計(jì)及emc設(shè)計(jì)-閱讀頁
2025-07-15 16:29本頁面
【正文】 Cmax: .≈fmax, 一般規(guī)則：maximize the distributed capacitance in the DC power bus.minimize the series inductance of lumped decoupling capacitors. 多層PCB、表貼電容，串聯(lián)電感在何處？Preferred location for decoupling capacitor:①on the silicon chip。③directly above or below the IC package。 return planes。 177。為什么數(shù)字輸出會振鈴？多層PCB 的分層安排： Reducing conducted amp。 susceptibility磁輻射的證明：傳導(dǎo)和輻射發(fā)射噪聲的原因：DM電流驅(qū)動輻射舉例：（高速信號和I/O信號間的磁耦合）規(guī)則：l All low frequency (kHz) I/O lines need HF(MHz) decoupling to the signal return (ground) at the connector to reduce VDM.l The signal return (ground) needs a HF(MHz) connection to the metal chassis at the connector to reduce VCM.注意：Electrically unconnected (floating) metal can increase capacitive coupling and EM radiation, typical examples: heat sinks, mechanical parts, unused wires, crystal cans, capacitor cans.DM電壓驅(qū)動輻射：減小DM電壓推動輻射措施：l 減小DM電壓l 減小DM帶寬（增加tr）（加RC濾波）l 減小電容耦合（屏蔽）l 減小電纜上的ICM（在連接器處將PCB與金屬盒短接）（連接器上加旁路電容C）（連接器上串電感L）屏蔽電纜可能比非屏蔽電纜輻射更強(qiáng)，與屏蔽體的接法有關(guān)。 Place ponents on the board before determining connector pin assignments.216。 Divide the circuit board into different DC voltage areas (12 VDC area, 5 VDC area, etc.).216。 Do not allow different DC voltage planes to overlap one another.216。 Keep all connectors on the same edge of the board.216。 Keep all I/O drivers very close to the connector. Avoid letting the I/O lines e too far onto the board.216。 Locate ponents to minimize the length of high speed clock lines. DC Power Distribution216。 Maximize the distributed capacitance in the DC power bus. Ideally, use parallel power and return planes with a Z0 1Ω.216。 Provide at least one decoupling capacitor (1100nF) for each integrated circuit DC power pin. Provide bulk decoupling (μF) where the DC power es onto the board and at the output of each voltage regulator and DCDC convertor.216。 Current takes the path of least impedance. Above 10kHz this usually means the smallest loop area path.216。 Treat all critical signals as current loops. Check each critical loop area before the board is built.216。 No trace should be permitted to cross any gaps in the return plane.216。 The spacing between any trace and the board edge should not be less than the spacing to the return plane. Signal Integrity – Reducing Crosstalk and Distortion216。 Traces on adjacent layers should be oriented perpendicular to one another.216。 Rounding may indicate excessive capacitance.216。 Separate high current, low frequency (kHz) return paths (ground) from low current return paths. Connect the high and low current returns together at only one point.216。 Do not allow any electrically floating metal.216。 Connect all unused integrated circuit gate inputs to either return (ground) or +VDC. High Frequency Transmission Lines216。 Use a Z0 40Ω to minimize the drive current and a Z0 120Ω to reduce emission and susceptibility.216。 The time delay for the arrival of a reflection may indicate the distance to the impedance mismatch. Reducing Conducted and Radiated Emissions216。 Do not use gaps in the return plane, except to control the location of low frequency (kHz) currents.216。 Most low frequency (kHz) I/O lines need HF(MHz) decoupling to the signal return (Ground) at the connector to reduce VDM applied to the cable.216。 Use the longest rise time possible for all pulse signals.216。 Use the lowest clock frequency possible.216。 Tightly control the loop area of all high speed signals.216。 For filter capacitors to be effective near 100MHz, essentially zero lead length is required. An “X” style lead connection may be necessary for a shunt capacitor.58 / 5
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