【正文】 thus, full scale is 1023/1024 3 2 mA. The switching cell of Q3, Q4, Q5 and Q6 serves to steer the cell current either to ground (BIT 1 low) or to the DAC output (BIT 1 high). The entire switching cell carries the same current whether the bit is on or off, minimizing thermal transients and ground current errors. The logic threshold, which is generated from the positive supply (see Digital Logic Interface), is applied to one side of each cell. DIGITAL LOGIC INTERFACE All standard positive supply logic families interface easily with the AD561. The digital code is positive true binary (all bits high, Logic “1,” gives positive full scale output). The logic input load factor (100 nA max at Logic “1,” –25 mA max at Logic “0,” 3 pF capacitance), is less than one equivalent digital load for all logic families, including unbuffered CMOS. The digital threshold is set internally as a function of the positive supply, as shown in Figure 6. For most applications, connecting VCC to the positive logic supply will set the threshold at the proper level for maximum noise immunity. For nonstandard applications, refer to Figure 6 for threshold levels. Unmitted bit input lines will assume a “1” state (similar to TTL), but they are high impedance and subject to noise pickup. Unused digital inputs should be directly connected to ground or VCC, as desired. Figure 6. Digital Threshold vs. Positive Supply 。C. The negative reference level is inverted and scaled by A1 to give a + volt reference, which can be driven by the low positive supply. The AD561, packaged in the 16pin DIP, has the + volt reference (REF OUT) connected directly to the input of the control amplifier (REF IN). The buffered reference is not directly available externally except through the kW bipolar offset resistor. The kW scaling resistor and control amplifier A2 then force a 1 mA reference current to flow through reference transistor Q1, which has a relative emitter area of 8A. This is acplished by forcing the bottom of the ladder to the proper voltage. Since Q1 and Q2 have equal emitter areas and equal 5 kW emitter resistors, Q2 also carries 1 mA. The ladder voltage drop constrains Q7 (with area 4A) to carry only mA。 this data is then used to laser trim a pensating circuit to balance the overall TC to zero. The typical resulting TC is 0 to 177。5 V Buffered Bipolar Voltage Output Figure 4. 177。10 volt bipolar range with an additional external resistor as shown in Figure 4. A larger value trimmer is required to pensate for tolerance in the thin film resistors, which are trimmed to match the fullscale current. For best full scale temperature coefficient performance, the external resistors should have a TC of –50 ppm/176。 this capacitor is required to pensate for the 25 picofarad DAC output capacitance. UNIPOLAR CONFIGURATION This configuration, shown in Figure 2, will provide a unipolar 0 V to +10 V output range. STEP I . . . ZERO ADJUST Turn all bits OFF and adjust op amp trimmer, R1, until the output reads volts (1 LSB = mV). STEP 11. . . GAIN ADJUST Turn all bits ON and adjust 50 W gain trimmer, R2, until the output is volts. (Full scale is adjusted to 1 LSB less than nominal full scale of volts.) If a V full scale is desired (exactly 10 mV/bit), insert a 120 W resistor in series with R2. BIPOLAR CONFIGURATION This configuration, shown in Figure 3, will provide a bipolar output voltage from – to + volts, with positive full scale occurring with all bits ON (all 1s). STEP 1. . . ZERO ADJUST Turn ON MSB only, turn OFF all other bits. Adjust 50 W trimmer R3, to give output volts. For maximum resolution a 120 W resistor may be placed