畢業(yè)設(shè)計(jì)(論文)外文資料翻譯〔含原文〕(參考版)
2025-06-22 17:30本頁(yè)面
【正文】 附件2：外文原文The 64bit PCI Extension The 64bit PCI Extension This chapter describes the 64bit extension that permits masters and targets to perform eight byte transfers during each data phase. It also describes 64bit addressing used to address memory targets that reside above the 4GB boundary.1． 64bit Ata Transfers and 64bit Addressing: Seperate Capabilities The PCI specification provides a mechanism that permits a 64bit bus master to perform 64bit data transfers with a 64bit target. At the beginning of a transaction, the 64bit bus maser automatically senses if the responding target is a 64bit or a 32bit device. If it’s a 64bit device, up to eight bytes(a quadword) may be transferred during each data phase. Assuming a series of 0wait state data phases, throughput of 264Mbytes/second can be achieved at a bus speed of 33MHz(8 bytes/transfer x 33 million transfers/second) and 528Mbytes/second the responding target is a 32bit device, the bus master automatically senses this and steers all data to or from the target over the lower four data paths(AD[31:0]).The specification also defines 64bit memory addressing capability. This capability is only used to address memory targets that reside above the 4GB address boundary. Both 32and 64[bit bus masters can perform 64bit addressing. In addition, memory target(that reside over the 4GB address boundary) that respond to 64bit addressing can be implemented as either 32or 64bit targets.2． 64Bit Extension SignalsIn order to support the 64bit data transfer capability, the PCI bus implements an additional thirtynine pins:l REQ64 is asserted by a 64bit bus master to indicate that is would like to perform 64bit data has the same timing and duration a s the FRAME signal. The REQ64 signal line must be supplied with a pull up resistor on the system cannot be permitted to float when a 32bit bus master is performing a transaction.l ACK64 is asserted by a target in response to REQ64 assertion by the master (if the target supports 64bit data transfers).ACK64 has the same timing and duration as DEVSEL(but ACK64 must not be asserted unless REQ64 is asserted by the initiator).Like REQ64,the AcK64 signal line must also be supplied with a pullup resistor on the system cannot be permitted to float when a 32bit device si the target of transaction.l AD [63::32] prise the upper four address/data paths.l C/BE [7::4] prise the upper four mand/byte enable signals.l PAR64 is the parity bit that provides even parity for the upper four AD paths and the upper four C/BE signal lines.
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