現(xiàn)代計(jì)算機(jī)體系結(jié)構(gòu)研討-wenkub.com
2025-01-21 22:22 本頁(yè)面
【正文】 但 MFLOPS也并非可靠 ， 因?yàn)椴煌瑱C(jī)器上浮點(diǎn)運(yùn)算集不同 。 ? 核心程序 – 從真實(shí)程序中提取的較短的但很關(guān)鍵的代碼構(gòu)成。在軟件中做一次乘法需要 200個(gè)周期，而用硬件來(lái)實(shí)現(xiàn)只要 4個(gè)時(shí)鐘周期。 Time to do the task (Execution Time) – execution time, response time, latency 176。它著眼于機(jī)器級(jí)內(nèi)各事件的排序方式與控制機(jī)構(gòu)、各部件的功能以及各部件間的聯(lián)系。 176。 計(jì)算機(jī)體系結(jié)構(gòu) Y e a rTransistors1000100001000001000000100000001000000001970 1975 1980 1985 1990 1995 2023i 8 0 3 8 6i 4 0 0 4i 8 0 8 0P e n t i u mi 8 0 4 8 6i 8 0 2 8 6i 8 0 8 62. Technology Trends: Microprocessor Capacity CMOS improvements: ? Die size: 2X every 3 yrs ? Line width: halve / 7 yrs Alpha 21264: 15 million Pentium Pro: million PowerPC 620: million Alpha 21164: million Sparc Ultra: million Moore’s Law ISSCC 2023: 25M+ transistor processors (Intel) 計(jì)算機(jī)體系結(jié)構(gòu) Memory Capacity (Single Chip DRAM) s i zeY e a rBits10001000010000010000001000000010000000010000000001970 1975 1980 1985 1990 1995 2023year size(Mb) cyc time 1980 250 ns 1983 220 ns 1986 1 190 ns 1989 4 165 ns 1992 16 145 ns 1996 64 120 ns 2023 256 100 ns 計(jì)算機(jī)體系結(jié)構(gòu) Technology Trends (Summary) Capacity Speed (latency) Logic 2x in 3 years 2x in 3 years DRAM 4x in 3 years 2x in 10 years Disk 4x in 3 years 2x in 10 years 計(jì)算機(jī)體系結(jié)構(gòu) 386486P e n t i u m ( R )P e n t i u m P r o( R )P e n t i u m ( R ) IIM P C 7 5 0604+6046 0 1 , 6 0 321264S2126421164A2116421064A21066101001 , 0 0 01 0 , 0 0 01987 1989 1991 1993 1995 1997 1999 2023 2023 2023Mhz110100Gate Delays/ ClockI n t e lI BM Po w e r PCD ECG a t e d e l a y s / cl o ckP r o c e s s o r f r e q s c a l e s b y 2 X p e r g e n e r a t i o nProcessor frequency trend ? Frequency doubles each generation ? Number of gates/clock reduce by 25% 計(jì)算機(jī)體系結(jié)構(gòu) Processor Performance Trends 計(jì)算機(jī)體系結(jié)構(gòu) Professor Performance 計(jì)算機(jī)體系結(jié)構(gòu) Performance Trends － (Summary) ? 性能 : 提高 50％ per year （ 2X / 18 months) ? 性價(jià)比 : 提高 70% per year 計(jì)算機(jī)體系結(jié)構(gòu) Density Access Time(Gbits/cm2) (ns)DRAM 10DRAM (Logic) 10SRAM (Cache) D e n s i ty M a x . A v e . Po w e r C l o c k R a te(M g a te s / c m 2 ) (W / c m 2 ) (G H z )C u s to m 25 54 3St d . C e l l 10 27 1 . 5G a te A r r a y 5 18 1Si n g l e M a s k G A 2 . 5 1 2 . 5 0 . 7F PG A 0 . 4 4 . 5 0 . 2 5 未來(lái)可能達(dá)到的水平 Die Area: cm Voltage: V Technology: ?m 15 times denser than today times power density 5 times clock rate Silicon in 2023 計(jì)算機(jī)體系結(jié)構(gòu) 未來(lái)的熱點(diǎn)之一 Source: Richard Newton 計(jì)算機(jī)體系結(jié)構(gòu) 嵌入式微處理器 ? 什么是嵌入式微處理器 一種可編程處理器，產(chǎn)品的最終用戶不能訪問(wèn)其編程接口 ,用戶只能通過(guò)應(yīng)用程序與其交互 ? 例如 PDA 3COM Palm pilots 原先為嵌入式系統(tǒng)設(shè)計(jì)，后來(lái)將編程接口開(kāi)放轉(zhuǎn)向通用計(jì)算機(jī)系統(tǒng)
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