現(xiàn)代計(jì)算機(jī)體系結(jié)構(gòu)研討(編輯修改稿)
2025-02-10 22:22 本頁面
【文章內(nèi)容簡介】 um, MMX, ...) 指令集結(jié)構(gòu)舉例 計(jì)算機(jī)體系結(jié)構(gòu) ? 指令類型 – Load/Store – Computational – Jump and Branch – Floating Point ? coprocessor – Memory Management – Special R0 R31 PC HI LO OP OP OP rs rt rd sa funct rs rt immediate jump target 3 種指令格式 : all 32 bits wide Registers MIPS R3000 Instruction Set Architecture (Summary) 計(jì)算機(jī)體系結(jié)構(gòu) Logic Designer39。s View ISA Level FUs Interconnect ? 主要部件的容量和性能特征 – (., Registers, ALU, Shifters, Logic Units, ...) ? 這些部件的互連方式 ? 這些部件間所傳送的信息 ? 這些信息流是如何控制的 . ? FU的實(shí)現(xiàn)技術(shù)（以實(shí)現(xiàn) ISA)ISA ? Register Transfer Level (RTL) 描述 計(jì)算機(jī)組織 計(jì)算機(jī)體系結(jié)構(gòu) The Big Picture Control Datapath Memory Processor Input Output ? 計(jì)算機(jī)五大部件 (1946年以來） 計(jì)算機(jī)體系結(jié)構(gòu) Example Organization ? TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 Boot PROM Floatingpoint Unit Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface SuperSPARC L2 $ CC MBus Module MBus L64852 MBus control MS Adapter SBus DRAM Controller SBus DMA SCSI Ether STDIO serial kbd mouse audio RTC Floppy SBus Cards 計(jì)算機(jī)體系結(jié)構(gòu) 計(jì)算機(jī)系統(tǒng)的層次結(jié)構(gòu) ? 不同的抽象層所“看到”的機(jī)器特征不同 ? 隨著技術(shù)的發(fā)展，體系結(jié)構(gòu)的定義也在發(fā)生變化 ? 體系結(jié)構(gòu)的研究涉及設(shè)計(jì)，度量和評價三方面 I/O system Instr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware Datapath Control Layout 計(jì)算機(jī)體系結(jié)構(gòu) Computer Architecture Technology Programming Languages Operating Systems History Applications Cleverness 體系結(jié)構(gòu)發(fā)展的源動力 計(jì)算機(jī)體系結(jié)構(gòu) D e s i g nA n a l y s i s體系結(jié)構(gòu)設(shè)計(jì)是個循環(huán)的過程 : ? 在計(jì)算機(jī)系統(tǒng)的各個層次上搜索 可能的設(shè)計(jì)空間 Bad Ideas Creativity Good Ideas Mediocre Ideas Cost / Performance Analysis 計(jì)算機(jī)體系結(jié)構(gòu)設(shè)計(jì)過程 Instruction Set Architecture Pipelining, Hazard Resolution, Superscalar, Reordering, Prediction, Speculation, Vector, VLIW, DSP, Reconfiguration Addressing, Protection, Exception Handling L1 Cache L2 Cache DRAM Disks, WORM, Tape Coherence, Bandwidth, Latency Emerging Technologies Interleaving Bus protocols RAID VLSI Input/Output and Storage Memory Hierarchy Pipelining and Instruction Level Parallelism 計(jì)算機(jī)體系結(jié)構(gòu)研究的內(nèi)容 計(jì)算機(jī)體系結(jié)構(gòu) M Interconnection Network S P M P M P M P 176。 176。 176。 Topologies, Routing, Bandwidth, Latency, Reliability Network Interfaces Shared Memory, Message Passing, Data Parallelism ProcessorMemorySwitch Multiprocessors Networks and Interconnections 計(jì)算機(jī)體系結(jié)構(gòu)研究內(nèi)容（續(xù)） 計(jì)算機(jī)體系結(jié)構(gòu) Simulate New Designs and Organizations Technology Trends Evaluate Existing Systems for Bottlenecks Benchmarks Workloads Implement Next Generation System Implementation Complexity Analysis Design Imple mentation
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