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高度越高則傳導電流越大,但由于硅片表面高低落差增加,工藝控制的困難度也變大。柵 柵耦合作用增強了對溝道的靜電控制能力。 ?對于 PMOS器件遷移率的提高自于中心布里淵區(qū)重輕空穴能帶的分離,導致較低帶間散射,同時應力引起價帶結(jié)構(gòu)的畸變,空穴有效質(zhì)量降低,空穴遷移率增加 ?對于 100nm的器件 ,優(yōu)化應力設(shè)計提高載流子遷移率顯得非常重要 SIMIT 63 SMIC Hybrid orientation Technology (HOT), gives up to 65% improvement in PFET performance but increase the plexity and difficulty in processing and the cost in manufacturing Source: IBM 混合晶向技術(shù) (Hybrid Orientation Technology) SIMIT 64 SMIC 鍺硅源漏 PMOSFET器件 Intel: IEDM 2022 ?90 nm: 17% Ge ?65 nm: 23% Ge ?45 nm: 30% Ge PChannel MOSFET mobility much improved! SIMIT 65 SMIC Advanced MOSFET器件 Intel/IMEC: IEDM 2022 ILD PSi NWELL P WELL highk N+ N+ highk SiGe STI SiGe nMOS WF TaCx pMOS WF TaCx Ny Dual Nitride Stress Liner Compressive Tensile pMOS Halo nMOS Halo Low Resistance Al Fill ?Gate First Process ?High k Gate Dielectric (HfSiON) ?SDDM(Single Dielectric Dual Gate Metals) ?DSL (Dual Stress Liner) ?SMT (Stress Mobility Technology) ?Strained Silicon SiGe S/D Engineering SIMIT 66 SMIC 平面分離雙柵場效應晶體管( Planar Split DG MOSFET) 一種全新的平面分離雙柵金屬氧化物半導體場效應晶體管 , 該器件垂直于溝道方向的電場 EZ為一非均勻場。 (b) 全耗盡型 SOI MOSFET。 SIMIT 49 SMIC 短溝道效應 (Short Channel Effect) ?For long channel device, the gate is the primary terminal in supporting the inversion charge in the channel. ?The positively ionized donor atoms on the n+ drain side of the bodydrain pn+ junction also allows for some support of inversion charge in the channel. For large devices, the contribution of the drain in controlling the inversion layer in the channel is much smaller pared to the gate. ?However, as devices are scaled down in length, the drain has a larger percentage contribution in supporting inversion charge in the channel. This effect is known as “charge sharing” and effectively reduces the gate control over the channel of the device. ?The offstate leakage current will increase since the gate doesn’t have full control of turning the device off. ?“Gate control” is the most important concept in the physics of a transistor for proper operation. 短溝道效應的主要機制 ?次表面穿通 ?源漏電荷共享 ?漏致勢壘降低效應 SIMIT 50 SMIC 漏致勢壘降低效應 Drain Induced Barrier Lowering ?Michael Stockinger, ?With the drain bias is increased, the surface potential in the drain region increases. ?Additionally, the surface potential also increases into the drain side of the channel. This results in lowering of the thermal barrier that is supposed to be fully controlled by the gate. SIMIT 51 SMIC Influence of DIBL on Subthreshold and VT ?The reduction in surface potential, or energy barrier, is known as Drain Induced Barrier Lowering (DIBL). ?DIBL manifests itself in multiple ways in electrical characteristics of a transistor known as “Short Channel Effects.” SIMIT 52 SMIC ?SiON Scaling Running Out Of Atoms ?Poly Depletion Limits Inversion TOX Scaling Gate Dielectric Scaling Running Out Of Atoms SIMIT 53 SMIC 其中 k1和 k2為與光刻工藝相關(guān)的參數(shù)。 需要通過改進器件結(jié)構(gòu)加以抑制 。 Polish Thin oxidation Etch Remove mask SiNx SiO2 trench SIMIT 23 SMIC 典型 CMOS工藝流程模塊 Well Formation “ Well” is a doped region where MOSFET is formed Electrically isolated NMOS and PMOS transistors in separate wells fabricated on the same substrate in CMOS process Lithography steps define regions where wells are formed SIMIT 24 SMIC 典型 CMOS工藝流程模塊 Well Formation Change mask Nwell chain implantation Pwell chain implantation Mask Remove mask Anneal SIMIT 25 SMIC Ion Implantation Boundary SIMIT 26 SMIC ? Thermal process to rearrange atoms in silicon matrix and to remove defects in the material ? Often used after implantation to place dopant atoms to locations where they can bee “activated” ? In more advanced processes, performed at very rapid heating rates and short times to minimize diffusion transport – “Rapid Thermal Processing” (RTP) or “Rapid Thermal Annealing” (RTA) 熱退火 (Annealing) SIMIT 27 SMIC ? Atomistic view of doping with ion implantation, followed by annealing ? Before doping: atoms in silicon are arranged in an orderly crystalline structure ? After annealing: the crystalline order is restored, but with dopant atoms now occupying some locations formerly occupied by silicon atoms ? During implantation: dopant ions are “shot” into silicon and disrupt silicon crystal’s orderly arrangement Dopant ions 熱退火 (Annealing) SIMIT 28 SMIC 典型 CMOS工藝流程模塊 Gate Formation Typically made out of heavily doped polysilicon SIMIT 29 SM