【導(dǎo)讀】院系電子工程學院儀器系。完成日期2011年3月7日。咨詢應(yīng)用工程師-33關(guān)于直接數(shù)字頻率合成器的問題。直接數(shù)字頻率合成器DDS是一種產(chǎn)生模擬波形通常是正弦波的儀器這種儀。器是生成一個數(shù)字形式的時變信號然后執(zhí)行數(shù)字到模擬的轉(zhuǎn)換因為用一個DDS. 能夠準確地產(chǎn)生和控制各種頻率和輪廓的波形的能力已成為一個通用于多。個行業(yè)重要要求在通信系統(tǒng)中能否利用良好的雜散性提供低相位噪聲可變頻率。和低成本是重要的設(shè)計考慮因素頻率產(chǎn)生的多種可能性對設(shè)計師來說是開放的。從鎖相回路PLL極高頻率合成的基礎(chǔ)技術(shù)到以數(shù)模轉(zhuǎn)換器DAC的動態(tài)編制程序輸。出來產(chǎn)生低頻任意波形但是DDS技術(shù)迅速在解決頻率或波形產(chǎn)生的通信和工業(yè)。55V的電壓下工作工作具有25MHz的時鐘消耗的最大功率為30毫瓦。赫茲到高達400兆赫以1GHz的時鐘為準其低功耗低成本單一小包裝固有的優(yōu)良。DDS器件不僅限于單純的正弦波輸出圖2顯示了由AD9833產(chǎn)生的方三角和。攜帶的功能允許相位累加器在DDS過程作為一個相輪

　　

【正文】 noise jitter and spuriousfree dynamic range SFDR Phase noise is a measure dBcHz of the shortterm frequency instability of the oscillator It is measured as the singlesideband noise resulting from changes in frequency in decibels below the amplitude at the operating frequency of the oscillator using a 1Hz bandwidth at two or more frequency displacements from the operating frequency of the oscillator This measurement has particular application to performance in the analog munications industry Do DDS devices have good phase noise Noise in a sampled system depends on many factors Referenceclock jitter can be seen as phase noise on the fundamental signal in a DDS system and phase truncation may introduce an error level into the system depending on the code word chosen For a ratio that can be exactly expressed by a truncated binarycoded word there is no truncation error For ratios requiring more bits than are available the resulting phase noise truncation error results in spurs in a spectral plot Their magnitudes and distribution depends on the code word chosen The DAC also contributes to noise in the system DAC quantization or linearity errors will result in both noise and harmonics Figure 9 shows a phase noise plot for a typical DDS devicein this case an AD9834 What about jitter Jitter is the dynamic displacement of digital signal edges from their longterm average positions measured in degrees rms A perfect oscillator would have rising and falling edges occurring at precisely regular moments in time and would never vary This of course is impossible as even the best oscillators are constructed from real ponents with sources of noise and other imperfections A highquality lowphasenoise crystal oscillator will have jitter of less than 35 picoseconds ps of period jitter accumulated over many millions of clock edges Jitter in oscillators is caused by thermal noise instabilities in the oscillator electronics external interference through the power rails ground and even the output connections Other infuences include external magic or electric felds such as RF interference from nearby transmitters which can contribute jitter affecting the oscillators output Even a simple amplifer inverter or buffer will contribute jitter to a signal Thus the output of a DDS device will add a certain amount of jitter Since every clock will already have an intrinsic level of jitter choosing an oscillator with low jitter is critical to begin with Dividing down the frequency of a highfrequency clock is one way to reduce jitter With frequency division the same amount of jitter occurs within a longer period reducing its percentage of system time In general to reduce essential sources of jitter and avoid introducing additional sources one should use a stable reference clock avoid using signals and circuits that slew slowly and use the highest feasible reference frequency to allow increased oversampling SpuriousFree Dynamic Range SFDR refers to the ratio measured in decibels between the highest level of the fundamental signal and the highest level of any spurious signalincluding aliases and harmonically related frequency ponentsin the spectrum For the very best SFDR it is essential to begin with a highquality oscillator SFDR is an important specifcation in an application where the frequency spectrum is being shared with other munication channels and applications If a transmitters output sends spurious signals into other frequency bands they can corrupt or interrupt neighboring signals Typical output plots taken from an AD9834 10bit DDS with a 50MHz master clock are shown in Figure 10 In a the output frequency is exactly 13 of the master clock frequency MCLK Because of the judicious choice of frequencies there are no harmonic frequencies in the 25MHz window aliases are minimized and the spurious behavior appears excellent with all spurs at least 80 dB below the signal SFDR 80 dB The lower frequency setting in b has more points to shape the waveform but not enough for a really clean waveform and gives a more realistic picture the largest spur at the secondharmonic frequency is about 50 dB below the signal SFDR 50 dB Do you have tools that make it easier to program and predict the performance of the DDS The online interactive design tool is an assistant for selecting tuning words given a reference clock and desired output frequencies andor phases The required frequency is chosen and idealized output harmonics are shown after an external reconstruction flter has been applied An example is shown in Figure 11 Tabular data is also provided for the major images and harmonics How will these tools help me program the DDS All thats needed is the required frequency output and the systems reference clock frequency The design tool will output the full programming sequence required to program the part In the example in Figure 12 the MCLK is set to 25 MHz and the desired output frequency is set to 10 MHz Once the update button is pressed the full programming sequence to program the part is contained in the Init Sequence register How can I evaluate your DDS devices All DDS devices have an evaluation board available for purchase They e with dedicated software allowing the user to testevaluate the part easily within minutes of receiving the board A technical note acpanying each evaluation board contains schematic information and shows best remended boarddesign and layout practice 1