【導(dǎo)讀】等外部接口芯片器件的應(yīng)用。掉電保護(hù)功能；實(shí)現(xiàn)對(duì)單價(jià)的調(diào)整。按模擬傳感器信號(hào)的按鍵，顯示行駛里程與總金額。在軟件中實(shí)現(xiàn)起步價(jià)，單價(jià)。數(shù)碼管顯示起步里程、單價(jià)，總里程、總金額。設(shè)計(jì)的主要內(nèi)容是利用51單片機(jī)實(shí)現(xiàn)出租車(chē)計(jì)價(jià)器的功能。的控制也是相對(duì)容易，易于實(shí)現(xiàn)的。數(shù)碼管顯示的穩(wěn)定性雖不及液晶屏，但其價(jià)格比液晶屏便宜，由于本。設(shè)計(jì)簡(jiǎn)單，采用數(shù)碼管顯示較好。選用存儲(chǔ)器芯片AT24C02組成掉電保護(hù)電路。AT89S51單片機(jī)芯片采用40引腳的雙列直插封裝方式。AT24C02是一個(gè)CMOS標(biāo)準(zhǔn)的EEPROM存儲(chǔ)器，掉電時(shí)能保存數(shù)據(jù)。需付總金額；按下清零按鍵，數(shù)碼管全顯示零，以備下次計(jì)價(jià)。現(xiàn)在各大中城市出租車(chē)行業(yè)都已普及自動(dòng)計(jì)價(jià)器，所以計(jì)價(jià)器技術(shù)的發(fā)展已成定局。程計(jì)費(fèi)求得客戶(hù)用車(chē)的總費(fèi)用，并通過(guò)數(shù)碼管顯示相應(yīng)的里程及金額。我在本次設(shè)計(jì)中主要負(fù)責(zé)硬件工作。本電路以AT89S51單片機(jī)為中心，附加A44E霍。模擬出租車(chē)計(jì)價(jià)器設(shè)計(jì)：進(jìn)行里程顯示，預(yù)設(shè)起步價(jià)和起步公里數(shù)；行程按全程收費(fèi)，

　　

【正文】 by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with InSystem Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highlyflexible and costeffective solution to many embedded control applications. Features： Compatible with Products 4K Bytes of InSystem Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles to Operating Range Fully Static Operation: 0 Hz to 33 MHz Threelevel Program Memory Lock 128 x 8bit Internal RAM 32 Programmable I/O Lines Two 16bit Timer/Counters Six Interrupt Sources Full Duplex UART Serial Channel Lowpower Idle and Powerdown Modes Interrupt Recovery from Powerdown Mode Watchdog Timer Dual Data Pointer 畢業(yè)設(shè)計(jì) 第 頁(yè) 21 Poweroff Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode) Green (Pb/Halidefree) Packaging Option The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16bit timer/counters, a fivevector twolevel interrupt architecture, a full duplex serial port, onchip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Powerdown mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. VCC： Supply voltage (all packages except 42PDIP). GND： Ground (all packages except 42PDIP。 for 42PDIP GND connects only the logic core and the embedded program memory). VDD： Supply voltage for the 42PDIP which connects only the logic core and the embedded program memory. PWRVDD： Supply voltage for the 42PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage. PWRGND： Ground for the 42PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the mon silicon substrate, but not through 畢業(yè)設(shè)計(jì) 第 頁(yè) 22 any metal link. The application board MUST connect both GND and PWRGND to the board ground. Port 0： Port 0 is an 8bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, PO has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification. Port 1： Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pullups. Port 2： Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that uses 16bit addresses (MOVX@DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX@RI), Port 2 emits the contents of the P2 Special Function Register. 畢業(yè)設(shè)計(jì) 第 頁(yè) 23 Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 3： Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pullups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51， as shown in the following table. RST： Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG： Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise,