現(xiàn)代cmos工藝基本流程培訓課程-資料下載頁
2025-01-19 13:18本頁面
【正文】 ontact Plug Metal1 Photoresist IMD1 通孔刻蝕 ? 通孔刻蝕 –基于氟的 RIE，獲得垂直的側墻 –提供金屬層之間的連接 67 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 除去光刻膠 68 Tungsten Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug TiN和鎢淀積 ? TiN和鎢淀積 –同第一層互連 69 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug 鎢和 TiN拋光 ? 鎢和 TiN拋光 –同第一層互連 70 Trench Oxide Polysilicon Cross Section N Well P Well N+ Source/Drain P+ Source/Drain Spacer Contact Metal1 Via1 平面視圖 ? 完成通孔 71 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Metal2淀積 ? Metal2淀積 – 類似于 Metal1 – 厚度和寬度增加，連接更長的距離，承載更大的電流 72 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 W Via Plug Metal2 光刻膠成形 ? 光刻膠成形 –相鄰的金屬層連線方向垂直，減小層間的感應耦合 73 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 W Via Plug Metal2 Metal2刻蝕 ? Metal2刻蝕 –類似于 Metal1 74 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 除去光刻膠 75 Trench Oxide Polysilicon Cross Section N Well P Well N+ Source/Drain P+ Source/Drain Spacer Contact Metal1 Via1 Metal2 平面視圖 ? 完成第二層互連，后面的剖面圖將包括右上角的壓焊點 76 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Passivation Metal2 鈍化層淀積 ? 鈍化層淀積 – 多種可選的鈍化層， Si3N SiO2和聚酰亞胺等 – 保護電路免受刮擦、污染和受潮等 77 Silicon Substrate P+ Silicon Epi Layer P P Well N Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 W Via Plug Passivation Bond Pad Poly Gate Gate Oxide Silicide Spacer Metal2 鈍化層成形 ? 鈍化層成形 –壓焊點打開，提供外界對芯片的電接觸 78 Cross Section Trench Oxide N+ Source/Drain P+ Source/Drain Spacer Contact Metal1 Polysilicon Via1 +5V Supply VOUT N Well P Well Metal2 Ground Bond Pad VIN 平面視圖 ? 完成，顯示了電氣連接和部分壓焊點 79 完成 80 略有不同的另一個工藝流程 Vth校正注入 場氧化層 TiN 演講完畢，謝謝觀看！
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