【正文】 R38 10K 0805 14 R18 R21 R22 R23 R24 R17 R14 R15 R13 R20 R19 R31 R32 R33 1K 0805 16 R16 R29 R34 R12 R25 R26 R27 R28 R11 R5 R6 R7 R8 R9 R10 R4 1uF 0805 1 C6 3216 2 C43 C44 30pF 0805 1 C41 47uF 6032 4 C52 C53 C54 C49 510 0603 1 R39 511 0805 1 R37 ATERA_AS DIP10 1 C47 DB9 DB9FL 1 J1 DPY_7SEG_DP DPY_7SEG_DP 4 DS1 DS2 DS3 DS4 EP1C20F324C8 BGA324x18 1 U1 EPCS4 SOP8 1 S2 FBP1 3216 1 L1 FBP2 3216 1 L2 JTAG DIP10 1 S22 LED LED0805AK 9 D10 D9 D8 D7 D6 D5 D4 D3 D2 LT1085 TO2633P 2 UP1 UP2 MAX3232CDB DIP16 1 S3 NO POP 0805 2 R30 R35 NPN 1 Q1 SPEAKER SPEAKER 1 LS1 SW SPST ANJ1 1 S4 SWITCH_6 SW6 1 C48 SWPB SWPB 17 S17 S5 S11 S8 S14 S6 S12 S9 S15 S7 S13 S10 S16 S18 S20 S19 S21 SWSPST ANJ1 4 S25 S24 S23 S26 uF 0805 1 C7 X1 XTALSMD 1 CHow to Formalize FPGA Hardware DesignJan Hole?ek, Tom225。? Kratochv237。la, Vojtěch ?eh225。k,David ?afr225。nek, and Pavel ?ime?ek To sum up, whenever the setting to the registered signal is controlled by an edgeof a signal。Following the physical aspects of hardware, changes of values of signals occurwith some infinitesimal delay, so called delta delay [VHDL]. We have to pointout that we abstract from this delay whenever it does not affect the propertieswe verify. We call this kind of abstraction the zero delay abstraction. Thisabstraction relies on the same idea as the synchronous hypothesis known fromsynchronous languages [Esterel]. As this abstraction is very strict and can hidesome very critical aspects of hardware design, we will discuss it in details lateron in this report.From the behavioral point of view,we distinguish two basic elements of hardwaredesign – binational logic elements (andgates, orgates,...) and sequentiallogic elements (latches and flipflops). Values of signals in binational logicelements can be sensed only in the moment in which they occur. In particular,the binational logic elements instantaneously transform values from inputsignals to values of output signals. In contrary, the purpose of a sequential logicelement is to save a value of a signal over time. We call this kind of behaviorregistered behavior with respect to the fact that the sequential logic is posedfrom registers and other memory elements.The crucial observation of the registered behavior is that an assignment ofa value to a registered signal is always put in the context of a conditionalspecification. In other words, assignments to registered signals are guarded. If aparticular guarding condition does not hold, the value of the relevant registeredsignal remains the same. This conservative behavior takes its place here even ifthe value of the input signal, which has to be stored, has been possibly changed.Moreover, assigning to a registered signal may be controlled also by eventsoccurring in some clock signal. Details of this behavior will be discussed later.Here we would like to give examples of two most basic sequential logic elements– a latch and a flipflop circuits. We focus on highlighting differences in behaviorof these circuits. In Figure 1 there is an example of a level sensitive latch. TheVHDL process statement construction in this figure is the key part of definitionof the latches behavior. The circuit has two input signals – the data signalin and the signal gate. There is also one output signal out. The circuit issensitive on changes occurring in both its input signals. The behavior is suchthat whenever gate has high value then the output out changes asynchronously(instantaneously) with any change of the signal in. In all situations in whichgate is low, out is constant and retains its current value. As the most significantproperty, we highlight the asynchrony of the latch behavior. In other words, the signal gate acts as a gate guarding a direct connection between the signal inand the signal out. A sample timing diagram is depicted in the right part of thefigure. Another basic sequential logic elements are flipflops. Their behavior is similarto that of latches with one crucial difference. Unlike latches, a flipflop is sensitiveonly on the clock signal. Assigning a value to a flipflop is synchronous withticks of the clock. An example of an edge sensitive flipflop is in Figure 2.The expression of the ifstatement requires not only clk to be high, but also therising edge in that signal. The output out signal will be updated to the value ofin just only in the moment when clk turns from low to high. Correspondingtiming diagram visualizing a typical flipflop signal flow is depicted in Figure 2. With respect to parison of aspects of the circuits described above we distinguishtwo kinds of behavior of registered signals – the synchronous and theasynchronous behavior. In the following two examples we show how the synchronousand the asynchronous behavior can be bined. For the first example(Figure 3) we use a flipflop register with an asynchronous reset. In this case,the signal out is reset to low value whenever the reset signal turns to high.This behavior is absolutely independent of the clk signal. With respect to thein signal the circuit behaves as a flipflop. In Fig