【導讀】畢業(yè)設(shè)計（論文）單片機MSP430與PC機串口通訊設(shè)計。方便的在這樣的分布式控制系統(tǒng)中單片機與微機之間的多路通信是整個系統(tǒng)的。關(guān)鍵基于MSP430系列單片機自身優(yōu)越的性能以及其超低功耗的特點利用。MSP430F149的USART可以實現(xiàn)這種分布式多機通信功能在解決了與PC串口或其。他帶有串口的終端相連所需要的串口電平和邏輯關(guān)系的轉(zhuǎn)變之后選用。MSP430F149的異步模式UART用C語言完成下位機PC機接收和發(fā)送數(shù)據(jù)程序借。助VC60開發(fā)平臺并利用PComm軟件包完成上位機單片機的通信程序。文章介紹了美國TI公司新一代16位Flash型MSP430F149系列單片機的結(jié)。構(gòu)特性和功能詳細介紹了如何利用VC十60進行串口通訊程序的編制重點介紹了。某個子系統(tǒng)的監(jiān)控對整個系統(tǒng)中各點的監(jiān)測或各子系統(tǒng)的協(xié)調(diào)控制則由某一個。串口電平的雙向轉(zhuǎn)換MSP430F149該單片機屬于德州儀器公司MSP430F14X16X. 有16位RISC結(jié)構(gòu)16位寄存器和常數(shù)寄存器MSP430達到了最大的代碼效率數(shù)。6msMSP430F149帶有兩個16位定時器帶看門狗功能速度極快的8通道12位AD. 轉(zhuǎn)換器ADC帶內(nèi)部參考電壓采樣保持和自動掃描功能一個內(nèi)部

　　

【正文】 minated the external interface board and cable 2 The device is programmable via the work 3 Number of channels increased to 8 4 Supports fiber optic as well as copper link interfaces 5 Uses a larger Xilinx FPGA 300000 gate version 6 Upon powerup the FPGA is autoloaded from Flash 7 Upgraded the interface circuitry B Network Issues Using a tcpip work in a control system is often a concern due to the tcpip protocols unpredictable latency In the UNT application work latency does not present a problem The use of the work is only for configuration and status no realtime functions are required For example the work is used to configure a channel to decode a link event delay a specified time and then output a trigger pulse This configuration is usually done well before the actual link event is expected to e Another work consideration is cybersecurity and channel configuration control The UNT is fully programmable and configurable over the work Unauthorized access to the device by a malicious user might cause the controldataacquisition system to malfunction The current workinterface device used on the UNT does not have a builtin firewall The laboratorys cybersecurity infrastructure and in particular configuration of the work port can restrict access to only authorized users or puters Lantronix Inc has recently released a work interface device called the XportAR This includes work security features and will beconsidered for the next fabrication cycle IV HARDWARE DESIGN Fig 1 shows a block diagram for the UNT The physical assembly is modular so that portions of the system can be upgraded when the onboard silicon bees obsolete It consists of the chassis a 5 volt power supply and three circuit boards the Facility Clock Link Interface the Main Board and the Auxiliary Board The 4layer printed circuit boards were designed inhouse using a free software package ExpressPCB The Facility Clock Link Interface es in two models one for twinaxial cable and the other for fiber optic connections The link interface was separated from the main board so that different fiber optic ponents could be used anticipating a change in fiber optic technology Both types of interfaces provide electrical isolation to eliminate ground loops The Main Board contains the following Lantronix XportXe work interface module Texas Instruments MSP430 microcontroller MCU Xilinx SpartanIIE XC2S300E FPGA Flash PEROM programmable and erasable read only memory and 16 optoisolated timing signal inputs There are also several jumpers on the board that are used to inform the FPGA program about the configuration of the system for example which type of auxiliary board is attached The Type 1 Auxiliary Board contains 24 timing signal outputs three for each of the eight channels One output is pulse transformercoupled one is an optocoupler and the third is a nonisolated line driver A Device Morphing Due to the modular and reprogrammable nature of the UNT it can be programmed and reconfigured to support a variety of control and data acquisition functions that are vastly different from the initial timing application The first application of this is the Clock Encoder One of the Nuts primary functions is to decode encoded events off of the Facility Clock Link The Clock Encoder does the opposite it encodes events onto the link The FPGA has been programmed to implement the timing functions of the CAMAC model 401 Clock Encoder Another type of auxiliary board will be used a Type 2 Auxiliary Board Instead of 24 outputs this board will have 16 optoisolated timing signal inputs for a total of 32 inputs The FPGA pins that connect to the Auxiliary Board will be reconfigured from outputs to inputs Each input trigger pulse will immediately generate a programmable clock event onto the Facility Clock link The UNT will be able to simultaneously generate events onto two separate Facility Clock links each having a different carrier frequency This would be useful at NSTX where a 1MHz carrier is needed for legacy CAMAC clock decoders model 404 but UNT and MTS devices could use the enhanced timing capability offered by a 10 MHz carrier Additional programs for the FPGA could implement other functions such as a strobed digital input module a multichannel counter or a digital inputoutput device In summary the same basic physical device and development processes can be used to make the UNT suitable for a wide variety of control system applications The Auxiliary Board and the front panel will be tailored to each specific application V SOFTWARE DESIGN A wide range of software skills were required to develop UNT The software functions development tools and user programming interfaces will be described in this section A Device Software There are two processors in the UNT device the MCU and the FPGA In addition to powerup sequencing the MCU is used to interface three onboard ponents the work interface flash memory and the FPGA as shown in Fig 2 The MCU interprets the works ining Modbus TCPIP messages and if valid performs the requested action Typical actions are to send timing channel values to the FPGA for example to program a delay between a clock link event and an output trigger for a transient digitizer The interface also supports updownloading FPGA code to the PEROM Development tools used for the MCU code include Microsoft Inc Visual C editor download mgr mspgcc The GCC toolchain for the Texas Instruments MSP430 MCUs free open As described in the FPGA code is produced by first using a schematicentry tool The schematic is drawn and then converted to VHDL and then piled into a file of Srecords This binary image is transferred over the work or via JTAG into the flash PEROM The FPGA runs its code in hardware firmware so realtime performance is