【正文】 sh memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high voltage (12volt) or a lowvoltage (Vcc) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the highvoltage programming mode is patible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the highvoltage or lowvoltage programming mode enabled. The respective topside marking and device signature codes are listed in the following table.Vpp=12VVpp=5VTopSide MarkAT89C51xxxxyywwAT89C51xxxx5yywwSignature(030H)=1EH(031H)=51H(032H)=FFH(030H)=1EH(031H)=51H(032H)=05HThe AT89C51 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct bination of control signals.4. Raise /Vpp to 12V for the highvoltage programming mode. 5. Pulse ALE/ once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimed and typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Polling:The AT89C51 features Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Polling may begin any time after a write cycle has been initiated. Ready/: The progress of byte programming can also be monitored by the RDY/ output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper bination of control signals and by holding ALE/ low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be reprogrammed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming Interface:Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate bination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to pletion.外文資料譯文AT89C51的介紹主要性能參數(shù)：與MCS51產(chǎn)品指令系統(tǒng)完全兼容4k字節(jié)可重復(fù)擦寫Flash閃速存儲(chǔ)器1000次擦寫周期全靜態(tài)操作：0Hz24MHz三級(jí)加密程序存儲(chǔ)器128 8字節(jié)內(nèi)部RAM32個(gè)可編程I/O口線2個(gè)16位定時(shí)/計(jì)數(shù)器6個(gè)中斷源可編程串行UART通道低功耗空閑和掉電模式描述:AT89C51是一個(gè)低電壓，高性能CMOS 8位單片機(jī)帶有4K字節(jié)的可反復(fù)擦寫的程序存儲(chǔ)器（PENROM）。和128字節(jié)的存取數(shù)據(jù)存儲(chǔ)器（RAM），這種器件采用ATMEL公司的高密度、不容易丟失存儲(chǔ)技術(shù)生產(chǎn)，并且能夠與MCS51系列的單片機(jī)兼容。片內(nèi)含有8位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的AT89C51單片機(jī)能夠被應(yīng)用到控制領(lǐng)域中。AT89C51提供以下的功能標(biāo)準(zhǔn)：4K字節(jié)閃爍存儲(chǔ)器，128字節(jié)隨機(jī)存取數(shù)據(jù)存儲(chǔ)器，32個(gè)I/O口，2個(gè)16位定時(shí)/計(jì)數(shù)器，1個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，1個(gè)串行通信口，片內(nèi)震蕩器和時(shí)鐘電路。另外，AT89C51還可以進(jìn)行0HZ的靜態(tài)邏輯操作，并支持兩種軟件的節(jié)電模式。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)存儲(chǔ)器、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存隨機(jī)存取數(shù)據(jù)存儲(chǔ)器中的內(nèi)容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個(gè)硬件復(fù)位。引腳描述：VCC：電源電壓 GND：地P0口：P0口是一組8位漏極開路雙向I/O口，即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口時(shí)，每一個(gè)管腳都能夠驅(qū)動(dòng)8個(gè)TTL電路。當(dāng)“1”被寫入P0口時(shí)，每個(gè)管腳都能夠作為高阻抗輸入端。P0口還能夠在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，轉(zhuǎn)換地址和數(shù)據(jù)總線復(fù)用，并在這時(shí)激活內(nèi)部的上拉電阻。P0口在Flash編程時(shí)，P0口接收指令，在程序校驗(yàn)時(shí)，輸出指令，需要接電阻。P1口：P1口一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)端口寫“1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)可作為輸入口。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)輸出一個(gè)電流。Flash編程和程序校驗(yàn)時(shí)，P1口接收低8位地址。P2口：P2口是一個(gè)內(nèi)部帶有上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)端口寫“1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)，可作為輸入口。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流。在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口線上的內(nèi)容在整個(gè)運(yùn)行期間不變。Flash編程或程序校驗(yàn)時(shí)，P2口接收高位地址和其它控制信號(hào)。P3口：P3口是一組帶有內(nèi)部電阻的8位雙向I/O口，P3口輸出緩沖故可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)P3口寫如“1”時(shí)，它們被內(nèi)部電阻拉到高電平并可作為輸入端時(shí)，被外部拉低的P3口將用電阻輸出電流。P3口除了作為一般的I/O口外，更重要的用途是它的第二功能，如下表所示：端口引腳第二功能RXDTXDINT0INT1T0T1WRRDP3口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。RST：復(fù)位輸入。當(dāng)震蕩器工作時(shí)，RET引腳出現(xiàn)兩個(gè)機(jī)器周期以上的高電平將使單片機(jī)復(fù)位。ALE/：當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE以時(shí)鐘震蕩頻率的1/16輸出固定的正脈沖信號(hào)，因此它可對(duì)輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖時(shí)，F(xiàn)lash閃速存儲(chǔ)器編程時(shí)，這個(gè)引腳還用于輸入編程脈沖。如果必要，可對(duì)特殊寄存器區(qū)中的8EH單元的D0位置禁止ALE操作。這個(gè)位置后只有一條MOVX和MOVC指令A(yù)LE才會(huì)被應(yīng)用。此外，這個(gè)引腳會(huì)微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無效。PSEN：程序儲(chǔ)存允許輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51由外部程序存儲(chǔ)器讀取指令時(shí)，每個(gè)機(jī)器周期兩次PSEN 有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的PSEN 信號(hào)不出現(xiàn)。/Vpp:外部訪問允許。欲使中央處理器僅訪問外部程序存儲(chǔ)器，EA端必須保持低電平。需要注意的是：如果加密位LBI被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平，CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電壓Vpp，當(dāng)然這必須是該器件是使用12V編程電壓Vpp。XTAL1：震蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。XTAL2：震蕩器反相放大器的輸出端。時(shí)鐘振蕩器:AT89C51中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，如圖1所示。外接石英晶體及電容C1，C2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對(duì)外接電容C1，C2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會(huì)輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性。如果使用石英晶體，我們推薦電容使用30PF177。10PF，而如果使用陶瓷振蕩器建議選擇40PF177。10PF。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖2所示。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。由于外部時(shí)鐘信號(hào)是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。圖