【正文】 reference is being used, both the VREF and CREF pins should be decoupled with 100 nF capacitors to AGND. These decouplingcapacitors should be placed very close to the VREF and CREF pins. For specified performance, it is remended that when using an external reference, this reference should be between V and the analog supply AVDD. If the internal reference is required for use external to the MicroConverter, it should be buffered at the VREF pin and a 100 nF capacitor should be connected from this pin to AGND. The internal V is factory calibrated to an absolute accuracy of V 177。50 mV. It should also be noted that the internal VREF will remain powered down until either of the DACs or the ADC peripheral blocks arepowered on by their respective enable bits.(4).CalibrationThe ADC block also has four associated calibration SFRs. These SFR’s drive calibration logic ensuring optimum performance from the 12bit ADC at all times. As part of the poweron reset configuration, these SFRs are configured automatically and transparently from factory programmed calibration constants. In many applications use of factory programmed calibration constants will suffice。 however, these calibr ation SFRs may be overwritten by user code to further pensate for systemdependent offset and gain errors.The ADC block incorporates calibration hardware that ensures optimum performance from the ADC at all times. The calibration modes are exercised as part of the ADuC812 internal factory final test routines. The factory calibration results are stored in Flash memory and are automatically downloaded on any poweron reset event to initialize the ADC calibration registers. In many applications this autocalibration download function suffices. Alternatively, a device calibration can be easily initiated by user software to pensate for significant changes in operating conditions (CLK frequency, analog input range, reference voltage and supply voltages). This incircuit software calibration feature allows the user to remove various system and reference related errors(whether itbe internal or external reference) and to make use of the full dynamic range of the ADC by adjusting the analog input range of the part for a specific system. Contact Analog Devices, Inc. for further details on the implement ation of the software calibration routine in your applications. MODES OF OPERATION(1).Typical OperationOnce configured via the ADCCON 13 SFRs (shown previously) the ADC will convert the analog input and provide an ADC 12bit result word in the ADCDATAH/L SFRs. The top four bits of the ADCDATAH SFRwill be written with the channel selection bits to identify the channel result. The format of the ADC 12bit result word is shown in Figure 5.(2).ADC DMA ModeThe onchip ADC has been designed to run at a maximum speed of one sample every 5 μs (., 200 kHz sampling rate). Therefore, in an interrupt driven routine the user software is required to service the interrupt, read the ADC result and store the result for further post processing, all within 5 μs otherwise the next ADC sample could be lost. In applications where the ADuC812 cannot sustain the interrupt rate, an ADC DMA Mode is provided. The ADC DMA Mode is enabled via the DMA enable bit (), which allows the ADC to sample continuously as per configuration in ADCCON SFRs. Each sample result is written into an external Static RAM (mapped in the data memory space) without any interaction from the ADuC812 core. This mode ensures the ADuC812 can capture a contiguous sample stream even at full speed ADC update rates. Before enabling ADC DMA mode the user must first configure the external SRAM to which the ADC samples will be consists of writing the required ADC DMA channels into the channel ID bits (the topfour bits) in the external SRAM. A typical preconfiguration of external memory is shown in Figure 6. Once the external data memory has been preconfigured, the DMA address pointer (DMAP, DMAH and DMAL) SFRs are written. These SFRs should be written with the DMA start address in external memory. In Figure 6, for example, the DMAstart address is 000000H. The 3byte start address should be written in the following order: DMAL, DMAH and end of a DMA table is signified by writing “1111” into the channel selection bits field. The DMA Enable bit (, DMA) can now be set to initiate the DMA conversion and transfer of the results sequentially into externalmemory. Remember that the DMA mode will only progress if the user haspreconfigured the ADC conversion time and trigger modes via the ADCCON1 and 2 SFRs. The end of DMA conversion is signified by the ADC interrupt bit .At the end of ADC DMA Mode, the external data memory contains the new ADC conversion results as shown in Figure should be noted that the channel selection bits are still present in the result words to identify the individual conversion results.外文資料譯文ADuC812微控制器1． 一般說明 ADUC812是全集成的高性能的12位數(shù)據(jù)采集系統(tǒng)，它的單個芯片內(nèi)集成了高性能的自校準多通道ADC，兩個12位ADC以及可編程的8位（與8051兼容）MCU。片內(nèi)8KB的閃速/電檫除（Flash/EE）程序存儲器，640字節(jié)的閃速/電檫除數(shù)據(jù)器以及256字節(jié)數(shù)據(jù)SRAM，均由可編程內(nèi)核控制。另外MCU具有包括看門狗定時器、電源監(jiān)視器和ADC DAM功能，為多處理器接口和I/O擴展提供了32條可編程的I/O線、I2C兼容的SPI和標準UART串行口I/O等。MCU內(nèi)核和模擬轉(zhuǎn)換二者均有正常、空閑和掉電工作模式，有適用于低功率應(yīng)用的電源管理方案。在工業(yè)范圍內(nèi)，有3V和5V兩種規(guī)格電壓工作器件可供選擇。它有52條引腳，用扁平塑料四方形封裝。2．ADuC812單片機特點：◇ 模擬I/O: 8通道,高精度12位ADC； 片內(nèi)、40ppm/℃電壓基準； 高速200kHz； 高速ADC至RAM的DMA控制器； 兩個12位電壓輸出DAC； 片內(nèi)溫度傳感器功能。◇ 存儲器： 8KB片內(nèi)閃速/電擦除程序存儲器； 640字節(jié)片內(nèi)閃速/電擦除數(shù)據(jù)存儲器； 片內(nèi)電荷泵（不需要外部Vpp； 256字節(jié)片內(nèi)數(shù)據(jù)RAM； 16M外部數(shù)據(jù)地址空間； 64K外部程序地址空間?！?與8051兼容的內(nèi)核： 額定工作頻率12MHz（最大16MHz）； 3個16位定時器/計數(shù)器； 32條可編程的I/O線； 高電流驅(qū)動能力——端口3； 9個中斷源，兩個優(yōu)先級?！?電源： 用3V和5V電壓工作； 正常、空閑和掉電模式。◇ 片內(nèi)外圍設(shè)備： URAT串行I/O； 兩線（與I2C兼容）和SPI串行I/O； 看門狗定時器； 電源監(jiān)視器。3. ADuC812的結(jié)構(gòu)特點：ADuC812是高集成度的精度12位數(shù)據(jù)采集系統(tǒng)。在ADuC812的內(nèi)核中，集成了一個高性能8位MCU（與8051兼容），這個MCU帶有片內(nèi)可再編程的非易失性閃速/電檫除程序存儲器，并控制片內(nèi)多通道（8個輸入通道）的12位ADC。為了全面支持可編程的數(shù)據(jù)采集核心功能，芯片組合了數(shù)據(jù)采集系統(tǒng)的全部輔助功能模塊。這些輔助功能模塊包括用戶閃速/電檫除數(shù)據(jù)存儲器，看門狗定時器（WDT），電源監(jiān)視器（PSM）以及