【正文】 ‘0’。ELSEIF CLK39。EVENT AND CLK=‘1’THENIF CHECLK=‘1’ THENIF TCOU3=1010 THENTCOU3=1010。ELSEIF TCOU1=1001 AND TCOU2=1001 AND TCOU3=1001 THENTCOU1=0000。TCOU2=0000。TCOU3=1010。OUTEN1= ‘1’。ELSIF TCOUl=1010 AND TCOU2=1001 THENTCOU1=0000。T0002=0000。TCOU3=TCOU3+1ELSIF TCOU1=1001 THENTCOU1=0000。TCOU2=TCOU2+1。ELSE TCOU1=TCOU1+1。END IF。END IF。ELSETCOU1=0000。 TCOU2= 0000。 TCOU3=0000。END IF。END IF。END IF。END PROCESS。P2:PROCESS(RESET,CHECLK)BEGINIF RESET= ‘1’THENTKEEP1=0000。TKEEP2=0000。TKEEP3=0000。ELSEIF CHECLK39。EVENT AND CHECLK= ‘1’ THENOUTEN=OUTEN1。TKEEPI=TCOU1。TKEEP2(=TCOU2。TKEEP3=TCOU3。END IF。END IF。END PROCESS。END P。根據(jù)存儲模塊的流程圖，存儲模塊的具體的VHDL清單如下:LIBRARY IEEE。USE 。USE 。USE 。ENTITY IICCONTROL ISPORT (CLK, START, STOP, WREN, RDEN: IN STD_LOGIC。IIDATAIN1,IIDATAIN2,IIDATAIN3: IN STD_LOGIC_VECTOR(3 DOWNTO 0)。FLAG: OUT STD_LOGIC。SDA: OUT STD_LOGIC。SCL: OUT STD_LOGIC)。END IICCONTROL:ARCHITECTURE A OF IICCONTROL ISSIGNAL SDAREG: STD_LOGIC。SIGNAL SCLREG: STD_LOGIC。SIGNAL CMDREG: STD_LOGIC。SIGNAL SEL: STD_LOGIC_VECTOR(1 DOWNTO 0)。SIGNAL IIDATA: STD_LOGIC_VECTOR(3 DOWNTO 0)。SIGNAL IICDATA: STD_LOGIC_VECTOR(3 DOWNTO 0)。SIGNAL FINISHED: STD_LOGIC。SIGNAL REGDATA1,REGDATA2,REGDATA3:STD_LOGIC_VECTOR(3 DOWNTO 0)。TYPE STATES IS (TO, T1, T1A, T2, T3, T4, T4A, T5, T6)。SIGNAL STATE: STATES。BEGINP1:PROCESS(START,WREN)BEGINIF START= ‘1’ THENIF WREN= ‘I’ THENREGDATA1=IIDATAIN1。REGDATA2=IIDATAIN2。REGDATA3=IIDATAIN3。END IF。END IF。END PROCESS。P2:PROCESS (CLK, WREN, REGDATA1, REGDATA2, REGDATA3)BEGINIF WREN=‘1’ THEN SEL=00。ELSIF RISING_EDGE(CLK) THENSEL=SEL+01。CASE SEL ISWHEN 00=IIDATA=REGDATA1。WHEN O1=IIDATA=REGDATA2。WHEN 10=IIDATA=REGDATA3。WHEN OTHERS=IIDATA=Z。END CASE。END IF。END PROCESS。P3:PROCESS(RDEN)BEGINIF RDEN=‘1’ THENSDA=CLK。SCL=‘1’。CMDREG=‘1’。END IF。END PROCESS。P4:PROCESS(CMDREG)VARIABLE BIT: INTEGER :=0。BEGINIICDATA=IIDATA。IF CMDREG=‘1’THENSDAREG=IICDATA(3)。STATE=T0。ELSESDAREG=‘1’。END IF。SCLREG=CLK。CASE STATE ISWHEN T0=IF CMDREG= ‘1’ THENSDA=SDAREG。SCL=‘0’。STATE=T1。ELSESTATE=T0。END IF。WHEN T1=SCL=‘1’。SDA=SDAREG。STATE=TlA。WHEN TlA=SCL=‘1’。SDA=SDAREG。STATE=T2。WHEN T2=IICDATA(3 DOWNTO 0)=IICDATA(2 DOWNTO 0)amp。 ‘0’。SDA=SDAREG。SCL=‘0’。IF BIT=3 THENSTATE=T3。ELSESTATE=T0。END IF。WHEN T3=SDA=‘0’。STATE=T4。WHEN T4=SDA=‘039。SCL=‘139。STATE=T4A。WHEN T4A=SDA=‘0’。SCL=‘1’。STATE=T5。WHEN T5=SCL= ‘0’。STATE=T6。WHEN T6=SDA= ‘0’。STATE=T0。END CASE。BIT=BIT+1。FINISHED=‘1’。END PROCESS。P5:PROCESS (STOP, CLK, FINISHED)BEGINIF STOP=‘1’ THENIF FINISHED= ‘1’ THENIF (CLK’EVENT AND CLK=‘1’)THENFLAG= ‘1’。SCL=‘1’。SDA=CLK。END IF。END IF。END IF。END PROCESS。END A。顯示模塊的VHDL描述有以下兩個(gè)組件。首先，數(shù)據(jù)的存儲與計(jì)算都是采用的二進(jìn)制，但是要將其輸出至七段數(shù)碼管顯示時(shí)，必須提供一個(gè)電路模塊專門將二進(jìn)制數(shù)轉(zhuǎn)換成七段碼表示，即七段譯碼器的設(shè)計(jì)。程序清單如下:LIBRARY IEEE。USE 。USE 。USE 。ENTITY BIN2LED ISPORT(BIN: IN STD_LOGIC_VECTOR(3 DOWNTO 0)。LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0))。END BIN2LED。ARCHITECTURE ARCH OF BIN2LED ISBEGINWITH BIN SELECTLED=0110000 WHEN 0001，11101101 WHEN 0010，21111001 WHEN 0011，30110011 WHEN 0100，41011011 WHEN 0101，51011111 WHEN 0110，61110000 WHEN 0111，71111111 WHEN 1000，81111011 WHEN 1001，91111110 WHEN 0000，00110001 WHEN OTHERS。1END ARCH。其次此模塊還應(yīng)包括七段顯示器掃描輸出電路模塊，為了節(jié)省3個(gè)顯示器顯示所需的電流消耗，利用視覺暫留原理讓七段顯示器輪流顯示。三組輸出數(shù)字DATAOUTI,DATAOUT2, DATAOUT3由選擇線SEL控制，輪流輸出至DIGITOUT。程序代碼為:LIBRARY IEEE。USE 。USE 。USE . ALL。ENTITY DISPLAY1 ISPORT(SYSSTARTI,CLKDISP1:IN STD_LOGIC。DATAIN1,DATAIN2,DATAIN3: IN STD_LOGIC_VECTOR(6 DOWNTO 0)。GATE11, GATE21, GATE31:OUT STD_LOGIC。DIGITOUT1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0))。END DISPLAY1。ARCHITECTURE ARCH OF DISPLAY1 ISSIGNAL SEL: STD_LOGIC_VECTOR(1 DOWNTO 0)。BEGINPROCESS(SYSSTART1,CLKDISP1,DATAIN1,DATAIN2,DATAIN3)BEGINIF SYSSTARTI=‘1’ THEN SEL=00。ELSIF RISING_EDGE(CLKDISP1) THENSEL=SEL+01。CASE SEL ISWHEN 00 =DIGITOUT1=DATAIN1。GATE11=‘1’。GATE21=‘0’。GATE31=‘0’。WHEN O1 =DIGITOUT1=DATAIN2。GATE11=‘0’。GATE21=‘1’。GATE31=‘0’。WHEN 10 =DIGITOUT1=DATAIN3。GATE11=‘0’。GATE21=‘0’。GATE31=‘1’。WHEN OTHERS=DIGITOUT1=0110001。END CASE。END IF。END PROCESS。END ARCH。在以上兩個(gè)模塊生成以后，要調(diào)用這兩個(gè)底層模塊，生成顯示模塊。元件的聲明:是對底層模塊的說明，使之可以在其他模塊中被調(diào)用，聲明調(diào)用模塊的名稱(元件)以及模塊引腳信號。元件聲明如下:COMPONENT BIN2LED ISPORT(BIN: IN STD_LOGIC_VECTOR(3 DOWNTO 0)。LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0))。END COMPONENT。COMPONENT DISPLAY1 ISPORT(SYSSTART1,CLKDISP1:IN STD_LOGIC。DATAIN1,DATAIN2,DATAIN3: IN STD_LOGIC_VECTOR(6 DOWNTO 0)。GATE11, GATE21, GATE31:OUT STD_LOGIC。DIGITOUT1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0))。END COMPONENT。元件的例化:利用PORT MAP語句聲明元件的端口列表，端口列表可以采用位置關(guān)聯(lián)和名稱關(guān)聯(lián)，此處采用的是名稱關(guān)聯(lián)法來映射實(shí)參與形參，形參是調(diào)用元件本身的引腳，實(shí)參是例化元件對引出的引腳，其語法格式為:形參協(xié)實(shí)參。例化過程為:U1:BIN2LED PORT MAP(BIN=DATA1,LED=DATAIN12)。U2:BIN2LED PORT MAP(BIN=DATA2,LED=DATAIN22)。U3:BIN2LED PORT MAP(BIN=DATA3,LED=DATAIN32)。U4:DISPLAYIPORTMAP(SYSSTART1=SYSSTART,CLKDISP1=CLKDISP,DATAIN1=DATAIN12,DATAIN2=DATAIN22,DATAIN3=DATAIN32,GATE11=GATE1,GATE21=GATE2,GATE31=GATE3,DIGITOUT1=DIGITOUT)。這樣調(diào)用元件的引腳與DISPLAY模塊引腳的對應(yīng)關(guān)系就非常明了。:LIBRARY IEEE。USE 。USE 。USE 。ENTITY ZHENGTI ISPORT(CLK: IN STD_LOGIC。CHECLK:IN STD_LOGIC。RESET:IN STD_LOGIC。SYSSTART:IN STD_LOGIC。SDA: OUT STD_LOGIC。SCL:OUT STD_LOGIC。GATE1,GATE2,GATE3:OUT STD_LOGIC。DIGITOUT: OUT STD_LOGIC_VECTOR(6 DOWNTO 0))。END ZHENGTI。ARCHITECTURE ARCH OF ZHENGTI ISCOMPONENT KONGZHI3 ISPORT(RESET:IN STD_LOGIC。SYSSTART: IN STD_LOGIC。FLAG: IN STD_LOGIC。BASECLK: IN STD_LOGIC。RESETOUT:OUT STD_LOGIC。STOP: OUT STD_LOGIC。STARTCUNCHU:OUT STD_LOGIC)。END KONGZHI3。COMPONENT COUNTER ISPORT( RESET: IN STD_LOGIC。CLK: IN STD_LOGIC。CHECLK: IN STD_LOGIC。OUTEN:OUT STD_LOGIC。TKEEPI: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)。TKEEP2: OUT STD_LOGIC_VECTOR(3 DOWNTO