【正文】 ilog 設(shè)計(jì)[M],機(jī)械工業(yè)出版社，2022[14]華清遠(yuǎn)見嵌入式培訓(xùn)中心. FPGA 應(yīng)用開發(fā)入門與典型實(shí)例[M],人民郵電出版社，2022[15]羅苑棠. CPLD/FPGA 常用模塊與綜合系統(tǒng)設(shè)計(jì)實(shí)例精講[M],電子工業(yè)出版社，2022附 錄C 語言程序（產(chǎn)生正弦波程序）include include define pi 湖北經(jīng)濟(jì)學(xué)院本科畢業(yè)（設(shè)計(jì)）論文34main(){int i。double s。for(i=0。i1024。i++){s=sin(pi/4*8*i/1024)。printf(%d: %d。\n,i,(int)((s+1)*255/2))。}}VHDL 語言程序sin_rom 存儲(chǔ)器 megafunction wizard: %ROM: 1PORT% GENERATION: STANDARD VERSION: MODULE: altsyncram ============================================================ File Name: Megafunction Name(s): altsyncram Simulation Library Files(s): altera_mf ============================================================ ************************************************************ THIS IS A WIZARDGENERATED FILE. DO NOT EDIT THIS FILE! Build 222 10/21/2022 SJ Full Version ************************************************************Copyright (C) 19912022 Altera CorporationYour use of Altera Corporation39。s design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by 湖北經(jīng)濟(jì)學(xué)院本科畢業(yè)（設(shè)計(jì)）論文35Altera or its authorized distributors. Please refer to the applicable agreement for further details.LIBRARY ieee。USE 。LIBRARY altera_mf。USE 。ENTITY sin_rom ISPORT(address : IN STD_LOGIC_VECTOR (9 DOWNTO 0)。clock : IN STD_LOGIC 。q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0))。END sin_rom。ARCHITECTURE SYN OF sin_rom ISSIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0)。COMPONENT altsyncramGENERIC (address_aclr_a : STRING。clock_enable_input_a : STRING。clock_enable_output_a : STRING。init_file : STRING。intended_device_family : STRING。lpm_hint : STRING。lpm_type : STRING。numwords_a : NATURAL。operation_mode : STRING。outdata_aclr_a : STRING。outdata_reg_a : STRING。widthad_a : NATURAL。width_a : NATURAL。width_byteena_a : NATURAL)。湖北經(jīng)濟(jì)學(xué)院本科畢業(yè)（設(shè)計(jì)）論文36PORT (clock0 : IN STD_LOGIC 。address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0)。q_a: OUT STD_LOGIC_VECTOR (7 DOWNTO 0))。END COMPONENT。BEGINq = sub_wire0(7 DOWNTO 0)。altsyncram_ponent : altsyncramGENERIC MAP (address_aclr_a = NONE,clock_enable_input_a = BYPASS,clock_enable_output_a = BYPASS,init_file = ,intended_device_family = Cyclone III,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = altsyncram,numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_reg_a = CLOCK0,widthad_a = 10,width_a = 8,width_byteena_a = 1)PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0)。END SYN。 ============================================================ CNX file retrieval info ============================================================ Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC 0 Retrieval info: PRIVATE: AclrAddr NUMERIC 0 Retrieval info: PRIVATE: AclrByte NUMERIC 0湖北經(jīng)濟(jì)學(xué)院本科畢業(yè)（設(shè)計(jì)）論文37 Retrieval info: PRIVATE: AclrOutput NUMERIC 0 Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC 0 Retrieval info: PRIVATE: BYTE_SIZE NUMERIC 8 Retrieval info: PRIVATE: BlankMemory NUMERIC 0 Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC 0 Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC 0 Retrieval info: PRIVATE: Clken NUMERIC 0 Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC 0 Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING PORT_A Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC 0 Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING Cyclone III Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC 0 Retrieval info: PRIVATE: JTAG_ID STRING NONE Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC 0 Retrieval info: PRIVATE: MIFfilename STRING Retrieval info: PRIVATE: NUMWORDS_A NUMERIC 1024 Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC 0 Retrieval info: PRIVATE: RegAddr NUMERIC 1 Retrieval info: PRIVATE: RegOutput NUMERIC 1 Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING 0 Retrieval info: PRIVATE: SingleClock NUMERIC 1 Retrieval info: PRIVATE: UseDQRAM NUMERIC 0 Retrieval info: PRIVATE: WidthAddr NUMERIC 10 Retrieval info: PRIVATE: WidthData NUMERIC 8 Retrieval info: PRIVATE: rden NUMERIC 0 Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING NONE Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING BYPASS Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING BYPASS Retrieval info: CONSTANT: INIT_FILE STRING Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING Cyclone III Retrieval info: CONSTANT: LPM_HINT STRING ENABLE_RUNTIME_MOD=NO Retrieval info: CONSTANT: LPM_TYPE STRING altsyncram Retrieval info: CONSTANT: NUMWORDS_A NUMERIC 1024 Retrieval info: CONSTANT: OPERATION_MODE STRING ROM Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING NONE Retrieval info: CONSTANT: OUTDATA_REG_A STRING CLOCK0 Retrieval info: CONSTANT: WIDTHAD_A NUMERIC 10 Retrieval info: CONSTANT: WIDTH_A NUMERIC 8 Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC 1 Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0] Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]湖北經(jīng)濟(jì)學(xué)院本科畢業(yè)（設(shè)計(jì)）論文38 Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 Retrieval info: LIBRARY: altera_mf Retrieval info: GEN_FILE: TYPE_NORMAL TRUE Retrieval info: GEN_FILE: TYPE_NORMAL FALSE Retrieval info: GEN_FILE: TY