【正文】 DOWNTO 0)。SIGNAL HOUR_CUR : STD_LOGIC_VECTOR(4 DOWNTO 0)。SIGNAL MAS_DAYS : STD_LOGIC_VECTOR(4 DOWNTO 0)。SIGNAL MAX_DAYS : STD_LOGIC_VECTOR(4 DOWNTO 0)。SIGNAL MIN_CUR : STD_LOGIC_VECTOR(5 DOWNTO 0)。SIGNAL MON_CUR : STD_LOGIC_VECTOR(3 DOWNTO 0)。SIGNAL SEC_CUR : STD_LOGIC_VECTOR(5 DOWNTO 0)。SIGNAL SEL_OUT : STD_LOGIC_VECTOR(2 DOWNTO 0)。SIGNAL WEEK_CUR : STD_LOGIC_VECTOR(2 DOWNTO 0)。SIGNAL YEAR_CUR : STD_LOGIC_VECTOR(6 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(5 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC_VECTOR(5 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC_VECTOR(4 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC_VECTOR(4 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC_VECTOR(3 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC_VECTOR(6 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC_VECTOR(2 DOWNTO 0)。BEGIN LED_MIN = SYNTHESIZED_WIRE_2。LED_HOUR = SYNTHESIZED_WIRE_5。LED_SEC = SYNTHESIZED_WIRE_0。LED_DAY = SYNTHESIZED_WIRE_8。LED_MON = SYNTHESIZED_WIRE_11。LED_YEAR = SYNTHESIZED_WIRE_14。LED_WEEK = SYNTHESIZED_WIRE_17。B2V_INST : TZKZQPORT MAP(CLK_KEY = CLK_KEY, CURRUT_MONTH_DAYS = MAX_DAYS, DAY_CUR = DAY_CUR, HOUR_CUR = HOUR_CUR, KEY = KEY, MIN_CUR = MIN_CUR, MON_CUR = MON_CUR, SEC_CUR = SEC_CUR, WEEK_CUR = WEEK_CUR, YEAR_CUR = YEAR_CUR, SEC_EN = SYNTHESIZED_WIRE_0, MIN_EN = SYNTHESIZED_WIRE_2, HOUR_EN = SYNTHESIZED_WIRE_5, DAY_EN = SYNTHESIZED_WIRE_8, MON_EN = SYNTHESIZED_WIRE_11, YEAR_EN = SYNTHESIZED_WIRE_14, WEEK_EN = SYNTHESIZED_WIRE_17, DAY = SYNTHESIZED_WIRE_10, HOUR = SYNTHESIZED_WIRE_7, MIN = SYNTHESIZED_WIRE_4, MON = SYNTHESIZED_WIRE_13, SEC = SYNTHESIZED_WIRE_1, WEEK = SYNTHESIZED_WIRE_19, YEAR = SYNTHESIZED_WIRE_16)。B2V_INST1 : CNT60PORT MAP(LD = SYNTHESIZED_WIRE_0, CLK = CLK_SEC, DATA = SYNTHESIZED_WIRE_1, CO = SYNTHESIZED_WIRE_3, NUM = SEC_CUR)。B2V_INST2 : CNT60PORT MAP(LD = SYNTHESIZED_WIRE_2, CLK = SYNTHESIZED_WIRE_3, DATA = SYNTHESIZED_WIRE_4, CO = SYNTHESIZED_WIRE_6, NUM = MIN_CUR)。B2V_INST3 : CNT24PORT MAP(LD = SYNTHESIZED_WIRE_5, CLK = SYNTHESIZED_WIRE_6, DATA = SYNTHESIZED_WIRE_7, CO = SYNTHESIZED_WIRE_20, NUM = HOUR_CUR)。B2V_INST4 : CNT30APORT MAP(LD = SYNTHESIZED_WIRE_8, CLK = SYNTHESIZED_WIRE_20, DATA = SYNTHESIZED_WIRE_10, MONTH = MON_CUR, YEAR = YEAR_CUR, CO = SYNTHESIZED_WIRE_12, NUM = DAY_CUR)。B2V_INST5 : CNT12PORT MAP(LD = SYNTHESIZED_WIRE_11, CLK = SYNTHESIZED_WIRE_12, DATA = SYNTHESIZED_WIRE_13, CO = SYNTHESIZED_WIRE_15, NUM = MON_CUR)。B2V_INST6 : CNT100PORT MAP(LD = SYNTHESIZED_WIRE_14, CLK = SYNTHESIZED_WIRE_15, DATA = SYNTHESIZED_WIRE_16, NUM = YEAR_CUR)。B2V_INST7 : CNT7PORT MAP(LD = SYNTHESIZED_WIRE_17, CLK = SYNTHESIZED_WIRE_20, DATA = SYNTHESIZED_WIRE_19, NUM = WEEK_CUR)。B2V_INST8 : DISPLAYPORT MAP(CLK_SCAN = CLK_SCAN, DAY = DAY_CUR, HOUR = HOUR_CUR, MIN = MIN_CUR, MON = MON_CUR, SEC = SEC_CUR, WEEK = WEEK_CUR, YEAR = YEAR_CUR)。END。 八、系統(tǒng)仿真/硬件驗(yàn)證 、從圖6仿真圖可以直觀的看出，本源程序?qū)崿F(xiàn)了0到59的循環(huán)計(jì)數(shù)，每當(dāng)計(jì)2滿時(shí)，計(jì)數(shù)模塊就會(huì)輸出一個(gè)進(jìn)位信號(hào)。同時(shí)當(dāng)LD端有低電平輸入時(shí)，說明置數(shù)信號(hào)（LD）有效。將預(yù)置數(shù)送入計(jì)數(shù)結(jié)果中去并計(jì)數(shù)模塊從預(yù)置數(shù)開始重新計(jì)數(shù)。圖6 從圖7仿真圖可以直觀的看出，本程序首先要讀當(dāng)前年和月，在對(duì)該月的最大天數(shù)進(jìn)行判斷并將結(jié)果向外輸出。在正常計(jì)數(shù)過程中，本模塊電路實(shí)現(xiàn)了從0到最大天數(shù)的循環(huán)計(jì)數(shù)，每當(dāng)計(jì)數(shù)到最大值就會(huì)溢出，向前進(jìn)位。同時(shí)當(dāng)LD端有低電平時(shí)即置數(shù)信號(hào)有效，這時(shí)預(yù)置數(shù)就會(huì)送入計(jì)數(shù)結(jié)果中去，計(jì)數(shù)將從預(yù)置值重新累加計(jì)數(shù)。 圖7 由圖8仿真圖易看出，分別選擇對(duì)應(yīng)的輸入數(shù)據(jù)輸出，達(dá)到設(shè)計(jì)要求。 圖8 由圖9仿真圖可以看出，按下調(diào)整鍵，調(diào)整模式依次經(jīng)過了正常及調(diào)時(shí)的各個(gè)狀態(tài)，達(dá)到設(shè)計(jì)要求.圖9 TZKZQ、VHD仿真圖 系統(tǒng)的硬件驗(yàn)證通過系統(tǒng)的仿真和調(diào)試無誤后，連接好硬件電路，再將電源接上，將源程序燒寫到硬件電路中，通過觀察硬件電路的運(yùn)行情況很好，都能達(dá)到設(shè)計(jì)指標(biāo)，本次設(shè)計(jì)很難成功。九 設(shè)計(jì)技巧分析在顯示控制電路的設(shè)計(jì)中，利用動(dòng)態(tài)掃描顯示的原理，即簡(jiǎn)化了顯示譯碼驅(qū)動(dòng)電路的設(shè)計(jì)，有節(jié)約了硬件的I/O口，同時(shí)還減小了系統(tǒng)的驅(qū)動(dòng)電流及功耗等，在實(shí)際使用中非常有價(jià)值。在調(diào)整控制電路的設(shè)計(jì)中，通過讀入系統(tǒng)當(dāng)前工作的各種時(shí)間信息進(jìn)行自加調(diào)整，簡(jiǎn)化了預(yù)置值的設(shè)計(jì)，利用狀態(tài)機(jī)非常簡(jiǎn)單的實(shí)現(xiàn)了8鐘調(diào)整的循環(huán)變化。在計(jì)時(shí)電路的設(shè)計(jì)中，利用CNT60計(jì)時(shí)的模塊化，其他的計(jì)時(shí)模塊在此基礎(chǔ)上修改一點(diǎn)點(diǎn)就可以了，大大減輕了設(shè)計(jì)的工作量。 十 系統(tǒng)拓展思路對(duì)于系統(tǒng)的各種控制時(shí)鐘信號(hào)，可以通過分頻電路對(duì)一個(gè)給定的合適平率信號(hào)進(jìn)行分頻產(chǎn)生。設(shè)計(jì)系統(tǒng)工作的外圍電路，系統(tǒng)用方波信號(hào)源、直流工作電源、彩燈控制的驅(qū)動(dòng)電路除了要求設(shè)計(jì)調(diào)試程序、外圍電路外，還要求設(shè)計(jì)制作整個(gè)系統(tǒng)，包括PCB的制作 十一 設(shè)計(jì)心得體會(huì) 通過這次課程設(shè)計(jì)，我進(jìn)一步加深了對(duì)電子設(shè)計(jì)自動(dòng)化的了解。并進(jìn)一步熟練了對(duì)QuartusII軟件的操作。EDA這門課程再也不像學(xué)習(xí)理論般那么空洞，有了更加貼切的了解及運(yùn)用。在編寫程序的過程中，遇到了很多問題，使我發(fā)現(xiàn)自己以前學(xué)習(xí)上存在的不足。通過與同學(xué)探討和請(qǐng)教老師，終于把問題都解決了，并加深了對(duì)數(shù)字時(shí)鐘原理和設(shè)計(jì)思路的了解。同時(shí)我也掌握了做課程設(shè)計(jì)的一般流程，為以后的電子設(shè)計(jì)這塊積累了一定的經(jīng)驗(yàn)，為以后從事相關(guān)工作一些幫助。做課程設(shè)計(jì)時(shí)，先查閱相關(guān)知識(shí)，把原理吃透，確定一個(gè)大的設(shè)計(jì)方向，在按照這個(gè)方向分模塊的把要實(shí)現(xiàn)的功能用流程圖的形式展示。最后參照每個(gè)模塊把輸入和輸出引腳設(shè)定，運(yùn)用我們所學(xué)的VHDL語言進(jìn)行編程?？傊ㄟ^這次的設(shè)計(jì)，進(jìn)一步了解了EDA技術(shù)，收獲很大，對(duì)軟件編程、排錯(cuò)調(diào)試、相關(guān)儀器設(shè)備的使用技能等方面得到較全面的鍛煉和提高。