【正文】 Faster Compile but Possibly Lesser Design Performance ? Auto Fit – Compile Stops after Meeting Timing – Conserves CPU Time – Default for New Designs ? One Fitting Attempt Fitter Settings Copyright 169。 2022 Altera Corporation 88 Physical Synthesis ? ReSynthesis Based on Fitter Output ? Makes Incremental Changes that Improve Results for a Given Placement ? Compensates for Routing Delays from Fitter ? Types ? Combinational Logic ? Registers ? Register Duplication ? Register Retiming ? Effort ? Trades Performance vs Compile Time ? Normal, Extra or Fast Created/Modified Nodes Noted in Compilation Report Copyright 169。 2022 Altera Corporation 89 Combinational Logic ?Swaps LookUp Table (LUT) Ports within LEs to Reduce Critical Path LEs ?Allows LUT Duplication to Enable Further Optimizations on the Critical Path f g a b critical LUT LUT c d e LUT LUT f g a e c d b Copyright 169。 2022 Altera Corporation 90 Register Duplication ?High FanOut Register Is Duplicated amp。 Placed to Reduce Delay ? Combinational Logic May Also Be Duplicated N Copyright 169。 2022 Altera Corporation 91 Assignments ?Assignment Editor ?Example Assignments ?I/O Assignments amp。 Analysis ?Perform Analysis amp。 Elaboration before Obtaining Hierarchy amp。 Node Information Copyright 169。 2022 Altera Corporation 92 Assignment Editor (AE) ? Provides Spreadsheet Assignment Entry amp。 Display ? Can Copy amp。 Paste from Clipboard Sort on Columns Enable/Disable Individual Assignments Copyright 169。 2022 Altera Corporation 93 Invoke the Assignment Editor by Highlighting an Entity in the Hierarchy View amp。 Right Clicking Opening Assignment Editor Assignments Menu Copyright 169。 2022 Altera Corporation 94 Opening Assignment Editor (cont.) ? Locate to Assignment Editor from Message Window, Timing Report, etc. Copyright 169。 2022 Altera Corporation 95 Using Assignment Editor Select Assignment from DropDown Menu amp。 Set Value DoubleClick Cells to Edit or Type Name Directly Launches Node Finder Copyright 169。 2022 Altera Corporation 96 Editing Multiple Assignments ?Use Edit Bar Editing Multiple I/O Standards at Once Copyright 169。 2022 Altera Corporation 97 Search by Name Using Wildcards (? or *) List of Nodes in Selected Entity amp。 Lower Levels of Hierarchy Use Filter to Select the Nodes to Be Displayed Select Nodes on Left amp。 Use Arrows to Move to the Right Node Finder Locate Nodes in a Certain Level of Hierarchy Start Displays Nodes Meeting Search Criteria Copyright 169。 2022 Altera Corporation 98 AE Dynamic Checking ? Validity of Constraint Checked during Entry ? ColorCoded to Display Status ? Grey – Disabled ? Black – Applied ? Yellow – Assignment Warning ? Dark Red – Inplete ? Bright Red – Error/Illegal Value ? Green – Enter New Assignment Copyright 169。 2022 Altera Corporation 99 Assignment Editor Features ? Category Bar ? Selects Category of Assignments to View ? Ex. Pin Assignments, Timing Assignments ? Each Can Be Customized ? Node Filter Bar ? Filters Constraints Displayed Based on Node Name ? Information Bar ? Displays Description of Selected Cell or Assignment Copyright 169。 2022 Altera Corporation 100 AE Tcl Commands ? Equivalent Tcl Commands Are Displayed as Assignments Are Entered ? Manually Copy to Create Tcl Scripts ? Export Command (File Menu) Writes All Assignments to a Tcl File Message Window Copyright 169。 2022 Altera Corporation 101 Export CSV File Assignments (Excel) ?Export to CSV File (File Menu) ? Import Data into Excel Copyright 169。 2022 Altera Corporation 102 Example Assignments ?Optimization Technique ?PCI I/O ?Output Pin Load Copyright 169。 2022 Altera Corporation 103 OPTIMIZATION TECHNIQUE ? Selects Synthesis Optimization Goal ? Speed ? Balanced (Default) ? Area ? Applies Only to Hierarchical Entities ? Effects Synthesis amp。 Logic Mapping ? Only Applies to Quartus II Integrated Synthesis Copyright 169。 2022 Altera Corporation 104 PCI I/O ? Turns on PCI Compatibility for Pins ? Ignored If Applied to Anything other than a Pin or a TopLevel Design Entity ? Controls Clamping Diode Located in the I/O Elements Copyright 169。 2022 Altera Corporation 105 Output Pin Load ? Specifies Output Pin Loading in picoFarads (pF) ? Changes Default Loading Value of I/O Standard ? Changes tco of Output Pins ? Allows Designer to Accurately Model Board Conditions ? Must Be Applied to Output or Bidirectional Pins Copyright 169。 2022 Altera Corporation 106 Available Logic Options (Assignments) 1) Go to Quartus II Help (Index) 2) Type in “Logic Options” 3) Click on “l(fā)ist of” Supported Devices Shown for each Assignment Copyright 169。 2022 Altera Corporation 107 I/O (Pin) Assignments ?Pin Planner ?Assignment Editor ?Import from Spreadsheet in CSV Format ?QSF File ?Timing Closure Floorplan ? Shows Pin Pad Distances ? Shows Relationships with Core ?Scripting Copyright 169。 2022 Altera Corporation 108 Pin Planner ?Interactive Graphical Tool for Assigning Pins ? Drag amp。 Drop Pin Assignments ? Set Pin I/O Standards ?Three Sections ? Unassigned Pins List ? Package View ? Assigned Pins List Assignments Menu ? Pin Planner Copyright 169。 2022 Altera Corporation 109 Pin Planner Window Unassigned Pins List Package View (Top or Bottom) Assigned Pins List Copyright 169。 2022 Altera Corporation 110 Pin Planner Features ? Displays I/O Banks, VREF Groups amp。 Differential Pin Pairing ? Hides NonMigratable I/O Pins ? Allows Easy Creation of Reserved Pins ? Use Unassigned Pins List ? Has EasytoRead Pin Legend View ? Pin Legend I/O Banks amp。 Differential Pairing Copyright 169。 2022 Altera Corporation 111 A