[工學(xué)]iclayout3digitallayout-資料下載頁
2025-02-15 18:57本頁面
【正文】 Skew and Insertion Delay March 13, 2022 Digital Layout 45 因此，一旦時鐘網(wǎng)同步化以及任何大扇出網(wǎng)絡(luò)插入緩沖器后，需要將網(wǎng)絡(luò)列表重新編譯并進行模擬。 ? 首先完成邏輯單元的放置 。確保了芯片核心邏輯的 時序性能得到滿足。 March 13, 2022 Digital Layout 46 實現(xiàn)時鐘樹的主要步驟 ? 考慮邏輯單元的位置 ， 插入時鐘樹 。在合理的位置 插入緩沖單元來使時鐘延遲最小和走線最短。 ? 完成所有信號的布線 ， 優(yōu)化布線以滿足時序要求 。 Example: DEC Alpha 21164(EV5) ? 300 MHz clock ( million transistors on a mm die in micron CMOS technology) – single phase clock ? nF total clock load – Extensive use of dynamic logic ? 20 W (out of 50) in clock distribution work ? Two level clock distribution – Single 6 stage driver at the center of the chip – Secondary buffers drive the left and right sides of the clock grid in m3 and m4 ? Total equivalent driver size of 58 cm !! 48 C l oc k D r i ve r s21164 Clocking Tree 49 21164 Clocking ? 2 phase single wire clock, distributed globally ? 2 distributed driver channels – Reduced RC delay/skew – Improved thermal distribution – clock load – 58 cm final driver width ? Local inverters for latching ? Conditional clocks in caches to reduce power ? More plex race checking ? Device variation trise = tskew = 150ps tcycle= Clock waveform Location of clock driver on die predriver final drivers ? 2 Phase, with multiple conditional buffered clocks – nF clock load – 40 cm final driver width ? Local clocks can be gated “off” to save power ? Reduced load/skew ? Reduced thermal issues ? Multiple clocks plicate race checking EV6 (Alpha 21264) Clocking 600 MHz – micron CMOS trise = tskew = 50ps tcycle= Global clock waveform PL L51 21264 Clocking 52 EV7 Clock Hierarchy G C L K( C P U C o re )L2L_CLK(L2 Cache)L2R_CLK(L2 Cache)N C L K( M e m C t r l )D L LPLLS Y S C L KDLLDLL+ widely dispersed drivers + DLLs pensate static and lowfrequency variation + divides design and verification effort DLL design and verification is added work + tailored clocks Active Skew Management and Multiple Clock Domains
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