ftlcd原理ppt課件-資料下載頁(yè)
2025-01-14 03:20本頁(yè)面
【正文】 EMI and Less Number of Cable Wires ? High Skew Tolerance and Noise Margin ? High Image Quality and Low Cost ? Long Transmission Distance TMDSTM Link Receiver (Rx) Digital Monitor Recovery/ Deserializer C1 C2 Transmitter (Tx) Encoder/ Serializer Clk Gen C0 Clk 24 bit data Pixel Clock 3 Controls Serial data channels amp。 clock Clk Gen TMDSTM Performance 7 bits TX0 7 bits TX1 7 bits TX2 7 bits TX3 VS. DatatoData PanelLink? Skew Tolerance 10 bits TX2 10 bits TX0 10 bits TX1 XGA Tck = TBIT Window ClocktoData, DatatoData Skew Tolerance (LVDS) 1/3 TBIT Window PanelLink? Skew Tolerance ?DatatoData skew: 15ns @ 65MHz ?Datatoclock skew: Immune to any skew ?Clock is only a frequency reference ?Advanced data recovery/synchronizing circuit LVDS Skew Tolerance ?Datatodata skew: @ 65MHz ?Datatoclock skew: @ 65MHz ?Clock must be synchronous with data ?Primitive serialization and transmission scheme Conventional Panel 監(jiān)視器廠商 面板廠商 Panel + Drive IC Timing Controller (ASIC) Scaler IC 電源輸入 影像輸出 軟性電路板 薄膜液晶 監(jiān)視器外殼 訊號(hào)輸入 ADC Analog TMDS Receiver Digital OSD DCDC converter Inverter Power Supply DCDC converter Backlight 監(jiān)視器廠商 面板廠商 Panel + Drive IC Timing Controller (ASIC) Scaler IC 電源輸入 影像輸出 薄膜液晶 監(jiān)視器外殼 訊號(hào)輸入 ADC Analog TMDS Receiver Digital OSD DCDC converter Inverter Power Supply DCDC converter Backlight Smart Panel 監(jiān)視器廠商 面板廠商 Panel + Drive IC Timing Controller (ASIC) Scaler IC 電源輸入 影像輸出 薄膜液晶 監(jiān)視器外殼 訊號(hào)輸入 ADC Analog TMDS Receiver Digital OSD DCDC converter Inverter Power Supply DCDC converter Backlight Smart Integration Panel
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