introductiontocmosvlsidesignlogicaleffort-資料下載頁
2024-10-12 15:43本頁面
【導(dǎo)讀】Introduction. DelayinaLogicGate. Example. Summary. Benneedstodecide:. –Howmanystagestouse?3RC. 12psin180nmprocess. Delayhastwoponents. dfp??Delayhastwoponents. Effortdelayf=gh(.stageeffort). dpf??Delayhastwoponents. Effortdelayf=gh(.stageeffort). g:logicaleffort. –g?1forinverter. dfp??Delayhastwoponents. Effortdelayf=gh(.stageeffort). h:electricaleffort=Cout/Cin. dfp??Delayhastwoponents. Parasiticdelayp. dpf??Whatabout. NOR2?
【正文】 electrical and branching Electrical Effort: H = (32*3) / 10 = Branching Effort: B = 8 ? If we neglect logical effort (assume G = 1) Path Effort: F = GBH = Number of Stages: N = log4F = ? Try a 3stage design CMOS VLSI Design Logical Effort Slide 41 Gate Sizes amp。 Delay Logical Effort: G = Path Effort: F = Stage Effort: Path Delay: Gate sizes: z = y = A [ 3 ] A [ 3 ] A [ 2 ] A [ 2 ] A [ 1 ] A [ 1 ] A [ 0 ] A [ 0 ]w o r d [ 0 ]w o r d [ 1 5 ]9 6 u n it s o f w o r d li n e c a p a c it a n c e10 10 10 10 10 10 10 10y zy z?f ?D?CMOS VLSI Design Logical Effort Slide 42 Gate Sizes amp。 Delay Logical Effort: G = 1 * 6/3 * 1 = 2 Path Effort: F = GBH = 154 Stage Effort: Path Delay: Gate sizes: z = 96*1/ = 18 y = 18*2/ = A [ 3 ] A [ 3 ] A [ 2 ] A [ 2 ] A [ 1 ] A [ 1 ] A [ 0 ] A [ 0 ]w o r d [ 0 ]w o r d [ 1 5 ]9 6 u n it s o f w o r d li n e c a p a c it a n c e10 10 10 10 10 10 10 10y zy z1 / 3? 5 . 3 6fF???3 1 4 1 2 2 . 1Df? ? ? ? ?CMOS VLSI Design Logical Effort Slide 43 Comparison ? Compare many alternatives with a spreadsheet Design N G P D NAND4INV 2 2 5 NAND2NOR2 2 20/9 4 INVNAND4INV 3 2 6 NAND4INVINVINV 4 2 7 NAND2NOR2INVINV 4 20/9 6 NAND2INVNAND2INV 4 16/9 6 INVNAND2INVNAND2INV 5 16/9 7 NAND2INVNAND2INVINVINV 6 16/9 8 CMOS VLSI Design Logical Effort Slide 44 Review of Definitions Term Stage Path number of stages logical effort electrical effort branching effort effort effort delay parasitic delay delay iGg??outpathinpathCCH ?NiBb??F GBH?FiDf??iPp??iFD d D P? ? ??outinCCh?o n p a th o ff p a tho n p a thCCCb ??f gh?fpd f p??g1CMOS VLSI Design Logical Effort Slide 45 Method of Logical Effort 1) Compute path effort 2) Estimate best number of stages 3) Sketch path with N stages 4) Estimate least delay 5) Determine best stage effort 6) Find gate sizes F GB H?4lo gNF?1ND N F P??1? NfF?? iii outingCCf?CMOS VLSI Design Logical Effort Slide 46 Limits of Logical Effort ? Chicken and egg problem – Need path to pute G – But don’t know number of stages without G ? Simplistic delay model – Neglects input rise time effects ? Interconnect – Iteration required in designs with wire ? Maximum speed only – Not minimum area/power for constrained delay CMOS VLSI Design Logical Effort Slide 47 Summary ? Logical effort is useful for thinking of delay in circuits – Numeric logical effort characterizes gates – NANDs are faster than NORs in CMOS – Paths are fastest when effort delays are ~4 – Path delay is weakly sensitive to stages, sizes – But using fewer stages doesn’t mean faster paths – Delay of path is about log4F FO4 inverter delays – Inverters and NAND2 best for driving large caps ? Provides language for discussing fast circuits – But requires practice to master
教學(xué)課件相關(guān)推薦
鄂ICP備17016276號-1