【正文】 tween alternatives – Emphasizes remarkable symmetries ? ? ?CMOS VLSI Design Logical Effort Slide 4 Example ? Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. ? Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unitsized transistors – True and plementary address inputs A[3:0] – Each input may drive 10 unitsized transistors ? Ben needs to decide: – How many stages to use? – How large should each gate be? – How fast can decoder operate? A [ 3 : 0 ] A [ 3 : 0 ]163 2 b it s16 words4:16 DecoderRegi s ter F i l eCMOS VLSI Design Logical Effort Slide 5 Delay in a Logic Gate ? Express delays in processindependent unit absdd??? ? 3RC ? 12 ps in 180 nm process 40 ps in mm process CMOS VLSI Design Logical Effort Slide 6 Delay in a Logic Gate ? Express delays in processindependent unit ? Delay has two ponents absd d??d fp??CMOS VLSI Design Logical Effort Slide 7 Delay in a Logic Gate ? Express delays in processindependent unit ? Delay has two ponents ? Effort delay f = gh (. stage effort) – Again has two ponents absdd??dpf??CMOS VLSI Design Logical Effort Slide 8 Delay in a Logic Gate ? Express delays in processindependent unit ? Delay has two ponents ? Effort delay f = gh (. stage effort) – Again has two ponents ? g: logical effort – Measures relative ability of gate to deliver current – g ? 1 for inverter absdd??d f p??CMOS VLSI Design Logical Effort Slide 9 Delay in a Logic Gate ? Express delays in processindependent unit ? Delay has two ponents ? Effort delay f = gh (. stage effort) – Again has two ponents ? h: electrical effort = Cout / Cin – Ratio of output to input capacitance – Sometimes called fanout absdd??d f p??CMOS VLSI Design Logical Effort Slide 10 Delay in a Logic Gate ? Express delays in processindependent unit ? Delay has two ponents ? Parasitic delay p – Represents delay of gate driving no load – Set by internal parasitic capacitance absdd??d pf??CMOS VLSI Design Logical Effort Slide 11 Delay Plots d = f + p = gh + p E l e c t r i c a l E f f o r t :h = Cout / CinNormalized Delay: dIn v e r t e r2 i n p u tN A N Dg =p =d =g =p =d =0 1 2 3 4 50123456CMOS VLSI Design Logical Effort Slide 12 Delay Plots d = f + p = gh + p ? What about NOR2? E l e c t r i c a l E f f o r t :h = Cout / CinNormalized Delay: dIn v e r t e r2 i n p u tN A N Dg = 1p = 1d = h + 1g = 4 / 3p = 2d = ( 4 / 3 ) h + 2E f f o r t D e l a y : fP a r a s i t i c D e l a y : p0 1 2 3 4 50