【導讀】信息經(jīng)過單線接口送入DSl820或從DSl820送出因此從主機CPU到DSl820僅需一條線(和地線)。Powerforreading,writing,andperformingtemperatureconversionscanbederivedfromthedatalineitselfwithnoneedforanexternalpower，讀溫度轉換可以由數(shù)據(jù)線本身來提供電源而不需要一個外部電源。由于每個DS18B20的包含一個唯一的序列號，因此任意多個DSl820可以存放在同一條單線總線上。這允許在不同的地方放置溫度傳感器。此功能可應用的地方包括空調(diào)環(huán)境控制，建筑物內(nèi)的溫度感應，設備或機器的過程監(jiān)控和控制。器件從單線的通信線上取得其電源，在信號線為高電平的時間周期內(nèi)，把能量貯存在內(nèi)部的電容器中，在單信號線為低電平的時間期內(nèi)斷開此電源，直到信號線變?yōu)楦唠娖街匦陆由霞纳娙蓦娫礊橹?。在單線接口情況下，在ROM操作未定建立之前不能使用存貯器和控制操作。這些命令對每一器件的64位激光ROM部分進行操作。TH或TL的最高有效位直接對應于16位溫度寄存器的符號位，如果溫度測量的結果高于TH或低于TL，那么器件內(nèi)告警標志將置位。每次溫度測量將更新告警標志，只要告警標志置位，DS1820將對告警搜索命令做出響應。

　　

【正文】 ed “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products.”The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all 0s.7 MEMORYThe DS18B20’s memory is organized as shown in Figure 8. The memory consists of a scratchpad RAM and a nonvolatile, electrically erasable RAM, which stores the high and low temperature triggers TH and TL, and the configuration register. The scratchpad helps insure data integrity when municating over the 1Wire bus. Data is first written to the scratchpad using the Write Scratchpad mand. It can then be verified by using the Read Scratchpad mand. After the data has been verified, a Copy Scratchpad mand will transfer the data to the nonvolatile RAM. This process insures data integrity when modifying memory. The DS18B20 EEPROM is rated for a minimum of 50,000 writes and 10 years data retention at T = +55176。C.The scratchpad is organized as eight bytes of memory. The first 2 bytes contain the LSB and the MSB of the measured temperature information, respectively. The third and fourth bytes are volatile copies of TH and TL and are refreshed with every poweron reset. The fifth byte is a volatile copy of the configuration register and is refreshed with every poweron reset. The configuration register will be explained in more detail later in this section of the datasheet. The sixth, seventh, and eighth bytes are used for internal putations, and thus will not read out any predictable pattern. It is imperative that one writes TH, TL, and config in succession。 . a write is not valid if one writes only to TH and TL, for example, and then issues a reset. If any of these bytes must be written, all three must be written before a reset is issued.There is a ninth byte which may be read with a Read Scratchpad [BEH] mand. This byte contains a cyclic redundancy check (CRC) byte which is the CRC over all of the eight previous bytes. This CRC is implemented in the fashion described in the section titled “CRC Generation”.7 READ/WRITE TIME SLOTS Write Time SlotsA write time slot is initiated when the host pulls the data line from a high logic level to a low logic level. There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write time slots must be a minimum of 60 us in duration with a minimum of a 1μs recovery time between individual write cycles.The DS18B20 samples the DQ line in a window of 15 us to 60 us after the DQ line falls. If the line is high, a Write 1 occurs. If the line is low, a Write 0 occurs.For the host to generate a Write 1 time slot, the data line must be pulled to a logic low level and then released, allowing the data line to pull up to a high level within 15 us after the start of the write time slot. For the host to generate a Write 0 time slot, the data line must be pulled to a logic low level and remain low for 60us. Read Time SlotsThe host generates read time slots when data is to be read from the DS18B20. A read time slot is initiated when the host pulls the data line from a logic high level to logic low level. The data line must remain at a low logic level for a minimum of 1 us。 output data from the DS18B20 is valid for 15 us after the falling edge of the read time slot. The host therefore must stop driving the DQ pin low in order to read its state 15 us from the start of the read slot (see Figure 12). By the end of the read time slot, the DQ pin will pull back high via the external pull up resistor. All read time slots must be a minimum of 60 us in duration with a minimum of a 1us recovery time between individual read slots.9