【正文】 r supplied with external VDD, a provision is made in the DS18B20 to signal the power supply scheme used. The bus master can determine if any DS18B20 are on the bus which require the strong pull up by sending a Skip ROM protocol, then issuing the read power supply mand. After this mand is issued, the master then issues read time slots. The DS18B20 will send back “0” on the 1Wire bus if it is parasite powered。 it will send back a “1” if it is powered from the VDD pin. If the master receives a “0,” it knows that it must supply the strong pull up on the DQ line during temperature conversions. See “Memory Command Functions” section for more detail on this mand protocol.3 OPERATION ALARM SIGNALINGAfter the DS18B20 has performed a temperature conversion, the temperature value is pared to the trigger values stored in TH and TL. Since these registers are 8bit only, bits 912 are ignored for parison. The most significant bit of TH or TL directly corresponds to the sign bit of the 16bit temperature register. If the result of a temperature measurement is higher than TH or lower than TL, an alarm flag inside the device is set. This flag is updated with every temperature measurement. As long as the alarm flag is set, the DS18B20 will respond to the alarm search mand. This allows many DS18B20s to be connected in parallel doing simultaneous temperature measurements. If somewhere the temperature exceeds the limits, the alarming device(s) can be identified and read immediately without having to read nonalarming devices.4 64BIT LASERED ROMEach DS18B20 contains a unique ROM code that is 64bits long. The first 8 bits are a 1Wire family code (DS18B20 code is 28h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. The 64bit ROM and ROM Function Control section allow the DS18B20 to operate as a 1Wire device and follow the 1Wire protocol detailed in the section “1Wire Bus System.” The functions required to control sections of the DS18B20 are not accessible until the ROM function protocol has been satisfied. This protocol is described in the ROM function protocol flowchart (Figure 5). The 1Wire bus master must first provide one of five ROM function mands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. After a ROM function sequence has been successfully executed, the functions specific to the DS18B20 are accessible and the bus master may then provide one of the six memory and control function mands.5 CRC GENERATIONThe DS18B20 has an 8bit CRC stored in the most significant byte of the 64bit ROM. The bus master can pute a CRC value from the first 56bits of the 64bit ROM and pare it to the value stored within the DS18B20 to determine if the ROM data has been received errorfree by the bus master. The equivalent polynomial function of this CRC is:The DS18B20 also generates an 8bit CRC value using the same polynomial function shown above and provides this value to the bus master to validate the transfer of data bytes. In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function given above and pare the calculated value to either the 8bit CRC value stored in the 64bit ROM portion of the DS18B20 (for ROM reads) or the 8bit CRC value puted within the DS18B20(which is read as a ninth byte when the scratchpad is read). The parison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry inside the DS18B20 that prevents a mand sequence from proceeding if the CRC stored in or calculated by the DS18B20 does not match the value generated by the bus master.The 1Wire CRC can be generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 6. Additional information about the Dallas 1Wire Cyclic Redundancy Check is available in Application Note 27 entitl