【導(dǎo)讀】TheAT89C52isalow-power,high-performanceCMOS8-bitmicroputerwith. ofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterrupt. VCC：Supplyvoltage.GND：Ground.andverification.

　　

【正文】 uction set patible with the MSC51 family. V. TEST HARDWARE The8052 Device Under Test (DUT) was tested as a ponent of a functional puter. Aside from DUT itself, the other ponents of the DUT puter were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hardwired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This DUT Board was connected to the Main Board by a short 60conductor ribbon cable. The Main Board had all other ponents required to plete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and munications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for manding of the DUT, downloading DUT Code to the DUT, and realtime error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup. VI. TEST SOFTWARE The8052 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the8052 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT puter. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established munications between the controller PC and the DUT. All test programs implemented: ? An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and munication to controller puter. ? An external realtime clock for data error tag. ? A watchdog routine designed to provide visual verification of8052 health and restart test code if necessary. ? A foulup routine to reset program counter if it wanders out of code space. ? An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission. The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured. Interrupt – This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically pared to a known value. Unexpected values were transmitted with register information. Logic – This test performed a series of logic and math putations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All mispares of putations and expected results were transmitted with other relevant register information. Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and mispares were corrected while error information and register values were transmitted. Program Counter The program counter was used to continuously fetch constants at various offsets in the code. Constants were pared with known values and mispares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of generalpurpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls generalpurpose register bank selection. Generalpurpose register banks were then pared with their expected values. All mispares were corrected and error information was transmitted. Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly pared the learned value with the current one. Mispares were reloaded with learned value and error information was transmitted. Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information. VII. TEST METHODOLOGY The DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with Boot/Serial Loader code. This code initialized the DUT Computer and interface through a serial connection to the controlling puter, the Test Controller. The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms)。 and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer39