【導讀】在ISA架構(gòu)中需要一組用于指令功能單。NiosII的處理器核心是由NiosII指令集硬件設計和本文中所描述的功能單。該處理器核心不包括外圍設備或外界邏輯連接。它僅包括NiosII體系結(jié)構(gòu)。NiosII體系結(jié)構(gòu)的功能單元由NiosII的基礎指令集構(gòu)成。然而，這并不表示任何。NiosII的實現(xiàn)是由特定的。所有定義的指令集的實現(xiàn)可以參考的NiosII處理器參。各個執(zhí)行情況如核心尺寸的減小或性能的提高都應達到特定的目。這種NiosII的架構(gòu)的靈活性允許不同的目標應用程序適應。硬件芯片卸下除法指令上，但會增加程序的操作執(zhí)行。達32個32位控制寄存器。狀態(tài)寄存器的CRS字段表示該寄存器為正在使用。映射寄存器組的一個典型功能是加速上下文切換。處理器有兩個特殊的指令rdprs和wrprs來移動寄存器組之間的數(shù)據(jù)。統(tǒng)內(nèi)核操作，并是可見的應用程序代碼。下面的＃pragma指令由NiosII編譯器忽略浮點指令，并由軟件實現(xiàn)。令的作用域是整個C文件。NiosII的指令集仿真器在NiosII集成開發(fā)環(huán)境不支持自定義指令。

　　

【正文】 I integrated development environment (IDE) does not support custom instructions. If you need to run your software on the ISS, disable the floatingpoint custom instructions in software with the pragma directives. All the floatingpoint custom instructions are singleprecision operations. Doubleprecision floatingpoint operations are implemented in software. When the floatingpoint custom instructions are not present, the Nios II piler treats floatingpoint constants as doubleprecision values. However, with the floatingpoint custom instructions, the Nios II piler treats floatingpoint constants as singleprecision numbers by default. This allows all floatingpoint expressions to be evaluated in hardware, at a possible cost in precision. If you do not wish floatingpoint constants tobe cast down to single precision values, append Lto each constant value, to instruct the piler to treat the constant as a doubleprecision floatingpoint value. In this case, if an expression contains a floatingpoint constant, each term in the expression is cast to double precision. As a result, the expression is puted with softwareimplemented doubleprecision arithmetic, at a possible cost in putation speed. With the GCC 4 piler tool chain, prepiled libraries are piled with doubleprecision floatingpoint constants. The behavior of prepiled floatingpoint library functions such as sin()and cos()is unaffected by the presence of the floatingpoint custom instructions. Reset and Debug Signals For more information on adding reset signals to the Nios II processor, refer to “ Advanced Features Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. For more information on the break vector and adding debug signals to the Nios II processor, refer to “ JTAG Debug Module Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. Exception and Interrupt Controllers The Nios II processor includes hardware for handling exceptions, including hardware interrupts. It also includes an optional external interrupt controller (EIC) interface. The EIC interface enables you to speed up interrupt handling in a plex system by adding a custom interrupt controller. Exception Controller The Nios II architecture provides a simple, nonvectored exception controller to handle all exception types. Each exception, including internal hardware interrupts, causes the processor to transfer execution to an exception address. An exception handler at this address determines the cause of the exception and dispatches an appropriate exception routine. Exception addresses are specified with the Nios II Processor parameter editor in Qsys and SOPC Builder. All exceptions are precise. Precise means that the processor has pleted execution of all instructions preceding the faulting instruction and not started execution of instructions following the faulting instruction. Precise exceptions allow the processor to resume program execution once the exception handler clears the exception. EIC Interface An EIC provides high performance hardware interrupts to reduce your program39。s interrupt latency. An EIC is typically used in conjunction with shadow register sets and when you need more than the 32 interrupts provided by the Nios II internal interrupt controller. The Nios II processor connects to an EIC through the EIC interface. When an EIC is present, the internal interrupt controller is not implemented。 Qsys and SOPC Builder connect interrupts to the EIC. The EIC selects among active interrupts and presents one interrupt to the Nios II processor, with interrupt handler address and register set selection information. The interrupt selection algorithm is specific to the EIC implementation, and is typically based on interrupt priorities. The Nios II processor does not depend on any specific interrupt prioritization scheme in the EIC. For every external interrupt, the EIC presents an interrupt level. The Nios II processor uses the interrupt level in determining when to service the interrupt. Any external interrupt can be configured as an NMI. NMIs are not masked by the , and have no interrupt level. An EIC can be softwareconfigurable. When the EIC interface and shadow register sets are implemented on the Nios II core, you must ensure that your software is built with the Nios II EDS version or higher. Earlier versions have an implementation of the eret instruction that is inpatible with shadow register sets. For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the Embedded Peripherals IP User Guide. For details about EIC usage, refer to “ Exception Processing” in the Programming Model chapter of the Nios II Processor Reference Handbook. Internal Interrupt Controller The Nios II architecture supports 32 internal hardware interrupts. The processor core has 32 levelsensitive interrupt request (IRQ) inputs, irq0through irq31, providing a unique input for each interrupt source. IRQ priority is determined by software. The architecture supports nested interrupts. Your software can enable and disable any interrupt source individually through the ienable control register, which contains an interruptenable bit for each of the IRQ inputs. Software can enable and disable interrupts globally using the PIE bit of the status control register. A hardware interrupt is generated if and only if all of the following conditions are true: ■ The PIE bit of the status register is 1 ■ An interruptrequest input, irqn, is asserted ■ The corresponding bit nof the ienable register is 1 In SOPC Builder, the Nios II processor core offers an interrupt vector custom instruction, which accelerates interrupt vector dispatch to reduce your program’s interrupt latency. The inte