【文章內(nèi)容簡介】 將會(huì)很難順利地完成大學(xué)四年的學(xué)習(xí)和本次畢業(yè)設(shè)計(jì)。 該論文是在我的畢業(yè)設(shè)計(jì)指導(dǎo)老師 x老師的親切、熱心的指導(dǎo)下完成的。 x老師的熱心給予的完成畢業(yè)設(shè)計(jì)的動(dòng)力， x老師的幫助使我客服了諸多困難，最終在老師的指導(dǎo)下我完成了畢業(yè)設(shè)計(jì)，再次我要深深的感謝她。 同時(shí)，我還要感謝 x老師，在做畢業(yè)設(shè)計(jì)的過程中我深深的感到了在去年和 x老師一起學(xué)習(xí) Quartus2對于我的畢業(yè)設(shè)計(jì)是多么的有用。所以我要感謝 x老師。 在設(shè)計(jì)之初，我的迷茫曾一度讓我煩悶，不知道該怎么寫，不知道怎么下手，在這個(gè)困難時(shí)期，各位老師和同學(xué)給了我很大的幫助，使他們的幫助使我一步步的完成了畢業(yè)設(shè)計(jì)。在這里請接受我真誠的謝意！ 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 13 參考文獻(xiàn) [1] 劉建清，劉漢文，高光海，等，從零開始學(xué) CPLD和 VerilogHDL編程技術(shù) [M]，北京：國防工業(yè)出版社， 2021； [2] 楊春玲，朱敏，等，可編程邏輯器件應(yīng)用實(shí)踐 [M]，哈爾濱：哈爾濱工業(yè)大學(xué)出版社， 2021 [3] 馮濤，王程，等，可編程邏輯器件開發(fā)技術(shù) —— MAX+plus2入門與提高 [M]，北京：人民郵電出版社， 2021 [4] 杜海生，邢文等， FPG設(shè)計(jì)指南器件、工 具和流程 [M]，北京：人民郵電出版社， 2021 [5] 王輝，殷穎，陳婷，俞一鳴，等， MAX+plus2和 Quattur2應(yīng)用于技巧開發(fā) [M]，北京：機(jī)械工業(yè)出版社， 2021 [6] 張志剛，等， FPGA于 SOPC設(shè)計(jì)教程 —— DE2實(shí)踐，西安：西安電子科技大學(xué)出版社， 2021 [7] 夏宇聞，等， Verilog數(shù)字系統(tǒng)設(shè)計(jì)教程（第 2版） [M]，北京：北京航空航天大學(xué)出版社， 2021 [8] 鄭利浩，王荃，陳華鋒，等， FPGA數(shù)字邏輯設(shè)計(jì)教程 —— Verilog[M]，北京：電子工業(yè)出版社，2021 [9] 夏 宇聞，甘偉，等， Verilog HDL入門 (第 3版 )[M]，北京：北京航空航天大學(xué)出版社， 2021 [10]吳厚航，等，深入淺出玩轉(zhuǎn) FPGA[M]，北京：北京航空航天大學(xué)出版社， 2021 [11]吳繼華，王誠，等， Altera FPGA/CPLD設(shè)計(jì)（基礎(chǔ)篇），北京：人民郵電出版社， 2021 [12] EDA先鋒工作室，吳繼華，蔡海寧，王誠，等， Altera FPGA/CPLD設(shè)計(jì)（高級篇）（第 2版），北京：人民郵電出版社， 2021 [13]（美）沃爾夫（ Wolr,W.），等，基于 FPGA的系統(tǒng)設(shè)計(jì) [M]， 北京：機(jī)械工業(yè)出版社， 2021 [14]姚遠(yuǎn)，李辰，等， FPGA應(yīng)用開發(fā)入門與典型實(shí)例（修訂版） [M]，北京：人民郵電出版社， 2021 [15]侯伯亨 ,等， VHDL硬件描述語言與數(shù)字邏輯電路設(shè)計(jì)（第三版） [M]，西安：西安電子科技大學(xué)出版社， 2021 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 14 附錄一 At present by the hardware description language (Verilog or VHDL) has done by a simple circuit design, can the prehensive and layout, rapid replication to test, is on the FPGA design verification of modern IC technical mainstream. These can edit ponent can be used to achieve some basic logic gate (such as AND, OR, XOR, NOT) OR a bit more plicated bination function such as decoder OR mathematical equations. In most of the FPGA inside, these editable ponents are contains memory ponents such as flipflop Flip flop) (or other more plete memory blocks. System according to need stylist can be connected by editable the FPGA internal logic, like connecting block a circuit test plate is placed on a chip. A after they leave the finished product FPGA logic blocks and connection can be changed according to the designers, so the FPGA can plete need logical functions. The FPGA in general than ASIC (special integrated chips) speed will slow, unable to perform plex designs, and consume more power. But they also have many advantages such as can quickly finished product, can be modified to correct an error in a programme and cheaper cost. Manufacturers might also offer cheap but editing ability is poor FPGA. Because these chips have more bad of the editable ability, so these design development is in ordinary FPGA pletion, and then on to design transferred to a similar to the chip ASIC. Another method is to use CPLD (plex programmable logic device prepare). Early in the mid 1980s PLD equipment in FPGA has root. CPLD and FPGA includes some relatively large number of programmable logic unit. CPLD logical gate 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 15 density in a logical units to tens of thousands, and FPGA is usually between in tens of thousands to millions of. The major difference between and FPGA CPLD their system structure. CPLD is a bit of restrictive structure. This structure by one or more editable results logical groups of the sum of gilead and some relatively low amounts of locking registers. The result is that lack of editing flexibility, but there can be expected to delay time and logic unit link units a high rate of advantages. And there are many connection FPGA is, so although let it unit can be more flexible editor, but the structure are much more plex. CPLD and FPGA another difference is most FPGA contain high levels of builtin module (such as adder and on timemultiplier) and builtin memory. A so the important difference is concerned, many new FPGA support full or part of the system in a configuration. Allow their design with system upgrades or dynamic reconfigured and change. Some FPGA can let equipment edit and part of the normal operation. Other parts continue. By the Logic element Array FPGA LCA (Array) such a Cell questions concept, internal including Configurable Logic module which CLB (Configurable questions) and Output Input module which Output IOB (Input) and internal attachment (Interconnect) three parts. Field programmable gates array (FPGA) is programmable devices. And the traditional logic circuit and the gate array (such as PAL GAL and CPLD device), pared with different structure, the FPGA, FPGA with small lookup table (16 x 1RAM) to realize the bination of logic, each lookup table connected to a D flipflop input and trigger again drive other logic circuit or driver I/O, which constitutes the assembly logic functions can be realized and realize the basic logic sequential logical function module, these module unit by using metal connection between interconnected or connected to the I/O modules. The logic is through FPGA inward. 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁 16 Current main FPGA is still based on lookup table technology, has far exceeded the previous version of the basic performance, and integrate the mon functions (such as RAM, clock management and the hardcore (DSP) ASIC type) module. The FPGA chip partially pleted by 7 to Lord, respectively: programmable input/output unit, basic programmable logic unit, plete clock management, embedded pieces type RAM, rich wiring resources, embedded bottom function units and inline dedicated hardware modules. The function of each module are as follows: 1. Programmable input/output unit (IOB) Programmable input/output unit referred to as I/O unit, is the interface with external circuit chip, plete different part electrical characteristics of input/output signal driver and matching requirements, its beckoned structure shown as shown in figure 12. The I/O within the FPGA in groups