【文章內(nèi)容簡介】 gnal assignment results in the corresponding event queue being modified to schedule the new event. signal line x 10ns 39。039。 Driver of 20ns 39。139。 signal x Event Values TimesNOTE: If no delay is specified, the signal event is scheduled for one infinitessimallysmall delta delay from the current time. The signal change will occur in the next simulation cycle. Examples(Assume current time is T) clock = not clock after 10ns。 change at T + 10ns databus = mem1 and mem2 after delay。 change at T + delay x = 39。139。 change to 39。139。 at time T + delta。Element delay models may be specified as either inertial or transport. Inertial delay is the default, and should be used in most cases. Inertial delay: The addition to an event queue of an event scheduled at time T automatically cancels any events in the queue scheduled to occur prior to time T, . any event shorter than the delay time is suppressed. Transport delay: Each new event is simply inserted into the event queue, . behavior. is that of a delay line. The keyword transport is used to indicate transport delays.Examples B = A after 5ns。 inertial delay C = transport A after 5 ns。 transport delay 5______15 17_________30 A _______| |_| |_____________ ____________________ B ___________| |_________ (Inertial Delay) _______ __________ C ___________| |_| |_________ (Transport Delay) 10 20 22 35Where there are multiple drivers for one signal, a resolution function must be provided to determine the value to be assigned to the signal from the values supplied by the multiple drivers. This allows simulation of buses with multiple sources/drivers. NOTE: Thestd_logicandstd_logic_vectortypes from the ieee library have predefined resolution functions: Example signal data_line: std_logic。 begin block1: data_line = 39。139。 one driver ... block2: data_line = 39。Z39。 2nd driverThe resolved value is 39。139。 since 39。139。 overrides a 39。Z39。 (floating) value. If the two values had been 39。139。 and 39。039。, the resolved value would have been 39。X39。, indicating an unknown result. CONCURRENT STATEMENTSConcurrent statements are included within architecture definitions and within block statements, representing concurrent behavior. within the modelled design unit. These statements are executed in an asynchronous manner, with no defined order, modeling the behavior. of independent hardware elements within a system. Concurrent Signal AssignmentA signal assignment statement represents a process that assigns values to signals. It has three basic formats. 1. A = B。A = B when condition1 elseC when condition2 else D when condition3 else E。 2. with expression select A = B when choice1, C when choice2, D when choice3, E when others。For each of the above, waveforms (timevalue pairs) can also be specified. Examples A = B after 10ns when condition1 else C after 12ns when condition2 else D after 11ns。 4input multiplexer (Choice is a 2bit vector) with Choice select Out = In0 after 2ns when 00, In1 after 2ns when 01, In2 after 2ns when 10, In3 after 2ns when 11。 2to4 decoder (Y = 4bit and A = 2bit vectors) Y = 0001 after 2ns when A = 00 else 0010 after 2ns when A = 01 else 0100 after 2ns when A = 10 else 1000 after 2ns 。 Tristate driver: (Y is logic4。 X is bit_vector) Y = 39。039。 after 1ns when En = 39。139。 and X = 39。039。 else 39。139。 after 1ns when En = 39。139。 and X = 39。139。 else 39。Z39。 after 1ns。 A is a 16bit vector A = (others = 39。039。)。 set all bits of A to 39。039。The keyword others in the last example indicates that all elements of A not explicitly listed are to be set to 39。039。. Process StatementAn independent sequential process represents the behavior. of some portion of a design. The body of a process is a list of sequential statements. Syntax: label: process (sensitivity list) ... local declarations ... begin ... sequential statements ... end process label。Example DFF: process (clock) begin if clock = 39。139。 then Q = D after 5ns。 QN = not D after 5ns。 end if。 end process DFF。The sequential statements in the process are executed in order, mencing with the beginning of simulation. After the last statement of a process has been executed, the process is repeated from the first statement, and continues to repeat until suspended. If the optional sensitivity list is given, a wait on ... statement is inserted after the last sequential statement, causing the process to be suspended at that point until there is an event on one of the signals in the list, at which time processing resumes with the first statement in the process. Block StatementAblockis a grouping of related concurrent statements that can be used in representing designs in a hierarchical manner. Syntax: label: block (guard expression) ... local declarations ... begin ... concurrent statements ... end block label。If agua