【文章內(nèi)容簡介】 y it, the design time can be saved. DECODERS（譯碼器） A decoder is a multiple_input, multiple_output logic circuit. The number of circuit input is n_bit and the number of circuit output is 2n.The most monly used output code is oneoutofm code, which contains m bits, where one bit is asserted at any time.INPUTSOUTPUTSENI1I0Y3Y2Y1Y0000000010000011010010110010011110002to4 binary decoder with an enable controlThe output functions:Y0=ENI1’ I0’ Y1=ENI1’ I0 Y2=ENI1I0’ Y3=ENI1 I02to4 binary decoder circuit with an enable control3bit Graycode output of a mechanical encoding diskDisk positionI2I1I0Binary decoder output0000Y0=145001Y1=190011Y2=1135010Y3=1180110Y4=1225111Y5=1270101Y6=1315100Y7=174X139 Dual 2to4 Decoderthe truth tableINPUTSOUTPUTSG_LBAY3_LY2_LY1_LY0_L1XX11110001110001110101010110110111The output functions:Y0_L=G_L+B+A=[G_L’B’A’]’Y1_L=G_L+B+A’=[G_L’B’A]’Y2_L=G_L+B’+A=[G_L’BA’]’Y3_L=G_L+B’+A’=[G_L’BA]’1/274X139 74X13974X138 3to8 Decoder The truth tableINPUTSOUTPUTSG1G2A_LG2B_LCBAY7_LY6_LY5_LY4_LY3_LY2_LY1_LY0_L0XXXXX11111111X1XXXX11111111XX1XXX111111111000001111111010000111111101100010111110111000111111011110010011101111100101110111111001101011111110011101111111Y0_L=EN_L+C+B+A =[ENC’B’A’]’Y1_L=EN_L+C+B+A’ =[ENC’B’A]’Y2_L=EN_L+C+B’+A =[ENC’BA’]’Y3_L=EN_L+C+B’+A’ =[ENC’BA]’Y4_L=EN_L+C’+B+A =[ENCB’A’]’Y5_L=EN_L+C’+B+A’ =[ENCB’A]’Y6_L=EN_L+C’+B’+A =[ENCBA’]’Y7_L=EN_L+C’+B’+A’ =[ENCBA]’EN_L= G1’+G2A_L+G2B_L 。 EN= G1G2A_L’G2B_L’ONE FACT:Y0=EN(I1’ I0’) Y1=EN(I1’ I0) Y2=EN(I1I0’) Y3=EN(I1 I0)Y0_L=G_L+B+A=[G_L’B’A’]’=[G_L+(B’A’)’]Y1_L=G_L+B+A’=[G_L’B’A]’ =[G_L+(B’A)’]Y2_L=G_L+B’+A=[G_L’BA’]’ =[G_L+(BA’)’]Y3_L=G_L+B’+A’=[G_L’BA]’ =[G_L+(BA)’]Y0_L = [G1G2A_L’G2B_L’C’B’A’]’=(EN_L) +(C’B’A’)’Y1_L= (EN_L)+(C’B’A)’Y2_L= (EN_L)+(C’BA’)’Y3_L= (EN_L)+(C’BA)’Y4_L=(EN_L)+(CB’A’)’Y5_L= (EN_L)+(CB’A)’Y6_L= (EN_L)+(CBA’)’Y7_L= (EN_L)+(CBA)’ONE OUTPUT OF DECODER MAP TO ONE MINTERM (OR THE NOT, IF THE OUTPUT IS LOW ACTIVE).A 4to16 decoder using two 74x13845 / 45A 5to32 decorder with 4 74x138 and 1/2 74x139EX1: The truth table shows in table 511. design the logic circuit with 74x138. INPUTSOUTPUTSCS_LRD_LA2A1A0BILL_LMARY_LKATE_LJOAN_LPAUL_LANNA_LFRED_LDAVE_L1XXXX11111111X1XXX1111111100000001111110000110011111000101110111100011111101110010011111011001011111110100110111111100011111011111BILL_L=[CS_L’RD_L’A2’A1’A0’]’ =[( CS_L+RD_L)’( A2’A1’A0’)]’MARY_L=[CS_L’RD_L’A2’A1’A0’+CS_L’RD_L’A2’A1’A0]’ =[(CSL+RD_L)’(A2’A1’A0’+A2’A1’A0)]’KATE_L=[(CSL+RD_L)’(A2’A1’A0+A2A1A0)]’JOAN_L=[( CS_L+RD_L)’( A2’A1A0’)]’PAUL_L=[( CS_L+RD_L)’( A2’A1A0)]’ANNA_L=[( CS_L+RD_L)’( A2A1’A0’)]’FRED_L=[( CS_L+RD_L)’( A2A1’A0)]’DAVE_L=[( CS_L+RD_L)’( A2A1A0’)]’EX2: To bluid the logic function by 74x138 F=ΣWXYZ(3,6,9,11,13,15)Let mi for the minterm i F=ΣWXYZ(3,6,9,11,13,15)=m3+m6+m9+m11+m13+m15 =[ m3’m6’m9’m11’m13’m15’]’SEVENSEGMENT DECODERSINPUT: 8421 BCD CODE, BI_L(BLANKING INPUT)OUTPUT: SEVENSEGMENT CODEINPUTSOUTPUTSBI_LDCBAabcdefg0XXXX0000000100001111110100010110000100101101101100111111001101000110011101011011011101100011111101111110000110001111111110011110011110100001101110110011001111000100011111011001011111100001111111110000000THE CIRCUIT SHOWN IN FIGTURE 545 PAGE 373 ENCODERSTHE OUTPUT CODE HAS FEWER BITS THAN THE INPUT CODE.BINARY ENCODERSINPUTS: 1 OUT OFM CODEOUTPUT: BINARY CODEY0=I7+I5+I3+I1Y1=I7+I6+I3+I2Y2=I7+I6+I5+I4THE TRUTH TABLE:INPUTSOUTPUTSI7I6I5I4I3I2I1I0Y2Y1Y0100000001110100000011000100000101000100001000000100001100000100