基于vhdl的dds信號發(fā)生器的綜合電子系統設計報告(編輯修改稿)
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【文章內容簡介】 =fclk_reg。 m=m_reg。 phase=phase_reg。end behave。 3. 相位累加器library IEEE。use 。use 。use 。entity phase_sum is generic(m_width:integer :=10)。 port(fclk:in std_logic。 m:in std_logic_vector(m_width1 downto 0)。 rest:in std_logic。 phase_out:out std_logic_vector(m_width1 downto 0))。end phase_sum。architecture behave of phase_sum is signal phase_reg: std_logic_vector(m_width1 downto 0)。 signal m_reg: std_logic_vector(m_width1 downto 0)。 begin process (fclk) begin if rest=39。039。 then phase_reg=0000000000。 elsif (fclk39。EVENT AND fclk=39。139。) then phase_reg=phase_reg+m_reg。 end if。 end process。 m_reg=m。 phase_out=phase_reg。end behave。 4. 10位加法器library IEEE。use 。use 。use 。entity add10 is port( phase_sum_in:in std_logic_vector (9 downto 0)。 phase_control:in std_logic_vector(9 downto 0)。 address:out std_logic_vector(9 downto 0))。end add10。architecture behave of add10 is signal address_reg:std_logic_vector(10 downto 0)。 signal phase_sum_reg:std_logic_vector(10 downto 0)。 signal phase_control_reg:std_logic_vector(10 downto 0)。 begin phase_sum_reg=39。039。amp。phase_sum_in。 phase_control_reg=39。039。amp。phase_control。 address_reg=phase_sum_reg+phase_control_reg。 address=address_reg(9 downto 0)。end behave。5. data_rom(調用LPM庫生成) megafunction wizard: %ROM: 1PORT% GENERATION: STANDARD VERSION: MODULE: altsyncram ============================================================ File Name: Megafunction Name(s): altsyncram Simulation Library Files(s): altera_mf ============================================================ ************************************************************ THIS IS A WIZARDGENERATED FILE. DO NOT EDIT THIS FILE! Build 151 09/26/2007 SJ Full Version ************************************************************Copyright (C) 19912007 Altera CorporationYour use of Altera Corporation39。s design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreeme
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