【文章內容簡介】 ted against SEU faults to get a reliable operation. Furthermore, despite the reduced number of bits on SFRs (Special Function Registers) used in this application (88 bits = 10 8bit registers + PC) pared to those used in the internal memory (944 bits = 108 words for matrices+ 10 words for variables and constants), they resulted in % of lost sequence faults (154 out of 344 faults that caused lost of sequence). This means, undoubtedly, that the protection of the SFRs in this processor is also required. Thus, from this analysis, the internal memory and the SFRs are defined as the sensitive zones of the 8051.4. Implementing Fault Tolerance in an 8051 DescriptionConsidering the results presented in last section, it clearly appears the need for some kind of protection of the microcontroller as a mean to guarantee the reliable operation of the whole system in radiation environments. In this work, the method chosen for protection is the implementation of a faulttolerant version of the 8051 by means of an Error Correcting Code in the sensitive area of the microcontroller (memory and internal registers, as shown in the last section). The main idea is to provide a VHDL description of the faulttolerant microprocessor that can be synthesized using existent tools.. 8051 StructureThe MSC8051 VHDL description presented at was reused to insert radiation tolerant test structures. The original code is entirely patible with the INTEL 8051 microprocessor in terms of instruction timing. As shown in Fig. 3, the microprocessor description is divided into six main blocks: a finite state machine that generates the states and controls the number of cycles for each instruction to guide the circuit operation。 a control part that provides some control signals for the data path。 an instruction part which generates the microcode word for each instruction。 the data path itself, including an ALU and some registers, the RAM and ROM memories.This original version of the 8051 microcontroller implements 25 instructions and uses 116 latches and 1075 LCs in a FLEX10K20 FPGA device. The clock frequency for this implementation is MHz.In terms of permanent faults, an atspeed selftestable version of this microcontroller has been implemented by inserting in each block a specific builtin selftest structure . The goal now is to modify the finite state machine flipflops, registers and memory blocks of the available VHDL description so that the whole microprocessor bees tolerant to transient faults due to the radiation effects.. Fault Tolerance TechniqueThe technique used in this work to detect and correct faults in memory cells is to assign a Hamming code to each memory element, and to perform the verification of the stored code every time this element is accessed. Since the implemented strategy concerning error recovery is pletely binational, it can be used for any subcircuit (memory block or internal register).In order to implement the Hamming code, two binational ponents were described in VHDL and inserted into the original description of 8051. The first ponent receives an nbit data and returns an mbit coded word (m = n +_log2 n .) The second ponent receives an mbit word and returns an nbit decoded and corrected data.The same ponents models for coding and decoding used in the memory were used to protect registers in the data path. Now, other instances of those models are used to code and decode ALU registers and accumulator, the stack pointer, the program counter, the instruction register, etc. Each time a register is accessed, it is decoded (and possibly corrected) before being used while the new data is coded before being stored. Since coding and decoding operations are pletely binational, there is no difference in terms of machine cycles needed for the execution of operations in the protected registers. This means the fault tolerant 8051 remains pletely patible with the original version in terms of timing. Of course, the clock frequency is altered, as it will be shown in Section . Fig. 5 shows the scheme of a protected register in the data path.. Synthesis of the Fault Tolerant 8051The use of presently available highdensity programmable circuits such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) is an attractive approach to fast prototyping and cost reduction. Indeed, these circuits can replace a high number of logic ponents allowing to build up plex designs on a single chip in a short developing time. The use of reprogrammable FPGAs along with the possibility to obtain the FPGA programming from high level language descriptions (such as VHDL) offers a flexible and low cost mean to pare the performances of different implementations for a given circuit.In order to validate the implemented structures, the faulttolerant VHDL description was synthesized in a FPGA environment. Although s