【文章內容簡介】 ersus an increase digital input value, the DAC is said to be missing codes. Thus, a 10 bit DAC that has a differential linearity of greater that 1 LSB is only accurate to 9 or less bits. The number of accurate output bits will specify the DDS spurious performance as 20log(2dl) where dl is the number differential linear bits.. Integral linearity is a measure of the DAC’s overall linear performance versus an ideal linear straight line. The straight line plot can be either a “best straight line” where DC offsets are possible at both the min and max outputs of the DAC, or the straight line can cross the end points of the min and max output values. A DAC will tend to have a characteristic curve that is traversed over the output range. Depending on the shape and symmetry (symmetry about the half way point of the DAC output) of this curve, output harmonics of the DDS fundamental output frequency will be produced. As these harmonics approach and cross the Nyquist frequency of Fclk/2, the harmonics bee under sampled and reflect back into the band of interest, 0 to Fclk/2. This problem is best illustrated by setting the NCO output to Fclk/4 plus a slight offset. The third harmonic will fall minus 3 folds the small offset from the fundamental and the second harmonic will cross the Nyquist frequency by 2 folds the small offset leaving a reflected image back in the band of interest A sample plot of this frequency setup is shown in Figure 5. Other DAC characteristic that will produce harmonic distortion is any disruption of the symmetry of the output wave form such as a different rise and fall time. These characteristics can typically be corrected by board ponents external to the DAC such as an RF transformer, board layout issues, attenuation pads etc. Given the plexities of the DDS system, engineers should consider implementing the design using separate devices for the numerically controlled oscillator, the digital to analog converter, and the low pass filter. This approach allows for signal observation at many points in the system, yet is pact enough to be practical as an endsolution. Alternatively, the discrete implementation can serve as a prototyping vehicle for a singlechip mixed signal ASIC. The author developed a version of the design using a Harris HI5721 evaluation board for the DAC. The NCO at the heart of the DDS design, and a random generator to test signal modulation, was implemented into about 65% of a QuickLogic field programmable gate array (FPGA). This FPGA, a QL16x24B 4000gate device, was chosen for its high performance, easeofuse, and powerful development tools. The NCO design included following: Developed in Verilog with the 8 bit CLA adder schematic captured and listed to Verilog 32 bit frequency word input 32 phase accumulator pipelined over 8 bits 8 bit phase moudulation word input 8 bit sine ROM lookup table The design was described mostly in Verilog, with an 8 bit carry look ahead adder modified from QuickLogic’s macro library listed to Verilog. The whole design cycle was less than four days (two days to describe the design and a day and a half to prototype the hardware). Everything worked perfectly the first time, with the design running at an impressive 45MHz as predicted by the software simulation tools. Plots used in the article to illustrate DDS performance parameters were provided from the test configuration. Figure 6 below shows the external IO interface to the NCO design .The function of each signal is described in the following table. Signal Function Table FREQWORD[31:0] This input is the frequency control word to the NCO. This word controls the phase accumulator rate, and thus, the output frequency of the DACOUT sinusoidal wave form. The output carrier frequency is calculated by the following : PHASEWORD[7:0] This input is the phase modulation control word to the NCO. This word controls the phase offset following the phase accumulator. This phase offset is used to phase modulate the output carrier. FWWRN This input is the low asserted frequency word write strobe. This strobe input registers the FREQWORD input on the rising edge. This strobe can be asynchronous to the SYSCLK. SYSCLK This is the reference system clock input to the NCO. This clock is the sampling clock of the output carrier. PNCLK This input is the pseudonoise generator clock input. This clock sets the data rate of the I and Q data outputs. RESETN This input is a low asserted global reset. When asserted, the internal phase and frequency word registers are cleared stopping the output carrier at 0 radians. DACOUT[7:0] This output is the sinusoidal DAC amplitude word. This word is valid on the rising edge of the DACCLK. The sinusoidal wave form output is represented by the following : f(t) = sin(2pFout(t) + Pout) DACCLK This output is the DAC clock strobe. This clock is the SYSCLK feed back to an output pin pensating for the latency of the NCO IO pins. The DACOUT amplitude words will be valid on the rising edge of the DACCLK. SIN This output is a single bit digital sine wave output. This sine wave output es from the MSB of the phase accumulator. The output frequency of this pin is controlled by the frequency word input. COS This output is a single bit digital cosine wave output. This cosine wave output es form the MSB and next most significant bit of the phase accumulator. The output frequency of this pin is controlled by the frequency word input. MSIN This output is a single bit digital sine wave output. This sine wave output es from the MSB of the phase modulator. The output frequency of this pin is controlled by the frequency word input and phase offset bythe phase word input. This sine wave output is the same as the SIN output with a phase offset of plus