【正文】 mplified example, the yellow cross illustrates a hardware prototype ECU that exceeds the ideals for power consumption and fails to meet the clock speed ideals. Because of the timetomarket constraint, the system architecture continues to be based upon the initial hardware prototype without adequate exploration of alternative choices. The end result of a hardware based development process is a suboptimum product that may miss the design targets. Conversely the green crosses show an alternative path to the optimum design solution. Several virtual systems are assembled and tested in the same timetomarket window. The final virtual system is ontarget for the design parameters, and the resulting work products from the virtual system are quickly converted into the physical product. Models of the system are initially created at a high level of abstraction, and, through the modelbased methodology, are driven to a full virtual implementation, then to an actual product. The modelbased methodology approach proposes the use of an architecture exploration tool to facilitate the rapid exploration of various CPUs, memories, and peripherals (system architecture). The system architecture is shown in the upper right of Figure 2 . The upper left of Figure 2 shows early revisions of the functional models of the system, known as system behavior. The system behavior and system architecture are bined, and an optimal solution is achieved by iteratively paring the performance of each partitioned alternative. The objective is to evaluate the various architectural and partitioning alternatives to gain a first order approximation of the optimum design. Some of the proposed EDA tools for architecture exploration offer the ability to model microcontroller architectures in only a few weeks duration. The simulations for architectural simulation may be only 80% accurate, but that is believed to be good enough to make the first order choices of microcontroller, timer architecture and memory usages. Our evaluations of the architectural exploration tools, however, indicate that the industry has not yet focused on solving microcontroller selection in a general way. As this paper presents, there is a tradeoff between simulation accuracy, cost of the modeling effort, and the time to model a new architecture. We are awaiting further tool maturation before expanding beyond paper evaluations of architecture exploration. The industry trend is toward building libraries of very accurate architecture models that execute the embedded software directly. A sufficient library of these detailed models can then be used to evaluate system architectures and also used for the final software development. We have focused our efforts on the lower left box of Figure 2。但仍將程序員束縛于潛在的硬件結(jié)構(gòu)中。 Verilog 和 VHDL等硬件描述語言的發(fā)明，以及與之相應的編譯器、仿真器和合成工具的創(chuàng) 作使得硬件設計者又從門類應用層面提升至寄存器轉(zhuǎn)換的應用層面上來了。其中， 70%的返工源于邏輯或是功能性錯誤，需要進行檢驗。這個方法可在去除阻礙傳統(tǒng)系統(tǒng)發(fā)展的弊病的同時，對硬件和軟件的相互作用做出早期的分析。在這個簡單的例子中，黃色的十字說明了一個硬件原型 ECU 超過了能量消耗的理想值，但未達到時鐘速度的理想值。系統(tǒng)結(jié)構(gòu)顯示在右上方。我們期待能有更為成熟的工具使我們不僅僅只局限于書面進行系統(tǒng)探尋，能進一步擴展到實際操作中去。高度準確的軟件仿真需要用到 32字節(jié)的 CPU虛擬處理器模型（ VPM）、微控制器邊緣模型、系統(tǒng) ASIC模型和環(huán)境刺